Via Technologies, Inc.

S3 Graphics Co., Ltd.

Boris Prokopenko

Timour T Paltashev

John Wakefield Brothers

Derek Gladding

Hsilin Huang

Liang Li

Konstantine I Iourcha

Yuanfeng Wang

Wen-Chung Chen

Jiangming Xu

Ping F Chen

Qunfeng (Fred) Liao

Timou Paltashev

Hsilin (Stephen) Huang

Derek Edward Davout Gladding

Included are embodiments of systems and methods for processing metacommands. In at least one exemplary embodiment a Graphics Processing Unit (GPU) includes a metaprocessor configured to process at least one context register, the metaprocessor including context management logic and a metaprocessor control register block coupled to the metaprocessor, the metaprocessor control register block configured to receive metaprocessor configuration data, the metaprocessor control register block further configured to define metacommand execution logic block behavior. Some embodiments include a Bus Interface Unit (BIU) configured to provide the access from a system processor to the metaprocessor and a GPU command stream processor configured to fetch a current context command stream and send commands for execution to a GPU pipeline and metaprocessor.

Metaprocessor for GPU control and synchronization in a multiprocessor environment

Included are systems and methods for supporting a plurality of Graphics Processing Units (GPUs). At least one embodiment of a system includes a context status register configured to send data related to a status of at least one context and a context switch configuration register configured to send instructions related to at least one event for the at least one context. At least one embodiment of a system includes a context status management component coupled to the context status register and the context switch configuration register.

Support of a plurality of graphic processing units

Included are embodiments of a Multiply-Accumulate Unit to process multiple format floating point operands. For short format operands, embodiments of the Multiply Accumulate Unit are configured to process data with twice the throughput as long and mixed format data. At least one embodiment can include a short exponent calculation component configured to receive short format data, a long exponent calculation component configured to receive long format data, and a mixed exponent calculation component configured to receive short exponent data, the mixed exponent calculation component further configured to received long format data. Embodiments also include a mantissa datapath configured for implementation to accommodate processing of long, mixed, and short floating point operands.

Dual mode floating point multiply accumulate unit

A command parser in a GPU is configured to schedule execution of received commands and includes a first input coupled to a scheduler. The first command parser input is configured to communicate bus interface commands to the command parser for execution. A second command parser input is coupled to a controller that receives ring buffer commands from the scheduler in association with a new or previously-partially executed ring buffer, or context, which are executed by the command parser. A third command parser input coupled to a command DMA component that receives DMA commands from the controller that are also contained in the new or previously-partially executed ring buffer, which are forwarded to the command parser for execution. The command parser forwards data corresponding to commands received on one or more the first, second, and third inputs via one or more outputs.

Graphics input command stream scheduling method and apparatus

Various embodiments for reducing external bandwidth requirements for transferring graphics data are included. One embodiment includes a system for reducing the external bandwidth requirements for transferring graphics data comprising a prediction error calculator configured to generate a prediction error matrix for a pixel tile of z-coordinate data, a bit length calculator configured to calculate the number of bits needed to store the prediction error matrix, a data encoder configured to encode the prediction error matrix into a compressed block and a packer configured to shift the compressed block in a single operation to an external memory location.

System and method for memory bandwidth compressor

A GPU pipeline is synchronized by sending a fence command from a first module to an addressed synchronization register pair. Fence command associated data may be stored in a fence register of the addressed register pair. A second module sends a wait command with associated data to the addressed register pair, which may be compared to the data in the fence register. If the fence register data is greater than or equal to the wait command associated data, the second module may be acknowledged for sending the wait command and released for processing other graphics operations. If the fence register data is less than the wait command associated data, the second module is stalled until subsequent receipt of a fence command having data that is greater than or equal to the wait command associated data, which may be written to a wait register associated to the addressed register pair.

GPU internal wait/fence synchronization method and apparatus

A method for high level synchronization between an application and a graphics pipeline comprises receiving an application instruction in an input stream at a predetermined component, such as a command stream processor (CSP), as sent by a central processing unit. The CSP may have a first portion coupled to a next component in the graphics pipeline and a second portion coupled to a plurality of components of the graphics pipeline. A command associated with the application instruction may be forwarded from the first portion to the next component in the graphics pipeline or some other component coupled thereto. The command may be received and thereafter executed. A response may be communicated on a feedback path to the second portion of the CSP. Nonlimiting exemplary application instructions that may be received and executed by the CSP include check surface fault, trap, wait, signal, stall, flip, and trigger.

GPU pipeline multiple level synchronization controller processor and method

An input stream of graphics primitives may be converted into to a predetermined output stream of graphics primitives by a processor in a graphics pipeline. The processor recognizes a predetermined sequence pattern in the input stream of graphics primitives to the processor. The processor determines whether the recognized sequence pattern can be converted into the one of the plurality of predetermined output streams of graphics primitives. If so, the processor identifies a number of vertices in the recognized sequence pattern and reorders the vertices into a predetermined output pattern. Thereafter, the processor outputs the predetermined output pattern corresponding to one or more graphics processing components.

Geometry primitive type conversion in a GPU pipeline

Systems for performing rasterization are described. At least one embodiment includes a span generator for performing rasterization. In accordance with such embodiments, the span generator comprises functionals representing a scissoring box, loaders configured to convert the functionals from a general form to a special case form, edge generators configured to read the special case form of the scissoring box, whereby the special case form simplifies calculations by the edge generators. The span generator further comprises sorters configured to compute the intersection of half-planes, wherein edges of the intersection are generated by the edge generators and a span buffer configured to temporarily store spans before tiling.

Method and apparatus for triangle rasterization with clipping and wire-frame mode support

A dynamically scheduled parallel graphics processor comprises a spreader that creates graphic objects for processing and assigns and distributes the created objects for processing to one or more execution blocks. Each execution block is coupled to the spreader and receives an assignment for processing a graphics object. The execution block pushes the object through each processing stage by scheduling the processing of the graphics object and executing instruction operations on the graphics object. The dynamically scheduled parallel graphics processor includes one or more fixed function units coupled to the spreader that are configured to execute one or more predetermined operations on a graphics object. An input/output unit is coupled to the spreader, the one or more fixed function units, and the plurality of execution blocks and is configured to provide access to memory external to the dynamically scheduled parallel graphics processor.

Multi-execution resource graphics processor

A system and method to manage data processing stages of a logical graphics pipeline comprises a number of execution blocks coupled together and to a global spreader that assigns graphics data entities for execution to the execution blocks. Each execution block has an entity descriptor table containing information about an assigned graphics data entity corresponding to allocation of the entity and a current processing stage associated with the entity. Each execution block includes a stage parser configured to establish pointers for the assigned graphics data entity to be processed on a next processing stage. A numerical processing unit is included and configured to execute floating point and integer instructions in association with the assigned graphics data entity. The execution blocks include a data move unit for data loads and moves within the execution block, with the global spreader, and with other execution blocks of the plurality of execution blocks.

System and method to manage data processing stages of a logical graphics pipeline

A low-cost high-speed programmable rasterizer accepting an input set of functionals representing a triangle, clipping planes and a scissoring box, and producing multiple spans per clock cycle as output. A Loader converts the input set from a general form to a special case form accepted by a set of Edge Generators, the restricted input format accepted by the Edge Generators contributing to their efficient hardware implementation.

An orthogonal data converter for converting the components of a sequential vector component flow to a parallel vector component flow. The data converter has an input rotator configured to rotate corresponding vector components of the sequential vector component flow by a prescribed amount, and a bank of register files configured to store the rotated vector components. The converter also has an output rotator configured to rotate the position of the vector components read from the bank of register files by a prescribed amount. A controller of the converter is operative to control the addressing of the bank of register files and the rotating of the vector components. In this regard, the controller is operative to write the vector components to the bank of register files in a prescribed order and read the vector components in a prescribed order to generate the parallel vector component flow.

Synchronous periodical orthogonal data converter

The computer graphics system is configured to improve the performance of a stencil shadow volume method for rendering shadows. The apparatus and methods utilize a combination of compressed and uncompressed stencil buffers in coordination with compressed and uncompressed depth data buffers. An uncompressed stencil buffer is capable of storing stencil shadow volume data for each pixel and a compressed stencil buffer is capable of storing stencil shadow volume data for a group of pixels. The compressed stencil buffer is utilized with a compressed stencil buffer cache to perform a stencil shadow volume operation more efficiently than present methods.

Apparatus and method of an improved stencil shadow volume operation

A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file, which are communicatively coupled to each other and arranged to accommodate shortened instruction words in multiple-issue processors. These components are arranged to permit greater access to registers by instructions, thereby permitting reduction of the word length, as compared to conventional very long instruction word (VLIW) processors.

Growing community of inventors

Milpitas, CA, United States of America

Boris Prokopenko