Analog Devices,inc.

Analog Devices Global

Analog Devices Global Unlimited Company

Analog Devices Technology

Sabine, Inc.

Boris Lerner

Gopal Karanam

Michael Meyer-Pundsack

John L Redford

Pradip Thaker

Harvey Weinberg

Kaushal Sanghai

Michael G Perkins

Jonathan Ephraim David Hurwitz

Jochen Schmitt

Arthur Joseph Kalb

Douglas Garde

Gary J Miller

Yogesh Jayaraman Sharma

Michael S Allen

Sefa Demirtas

Doran M Oster

Andrew James Higham

Satishchandra G Rao

Benno Kusstatscher

Guolin Pan

Steven L Cox

Rasekh Rifaat

Paul R Blanchard

Ning Yang

Pradip Thacker

Jiang Wu

David Miller

Praveen Sanjeev

Gokul Muthusamy

Sreejith Kazhayil

Robert Bushey

Gopal Gudhdur Karnam

Gokal Muthusamy

Gopal Gudhur Karnam

In an optical detection system, received light can be concentrated and presented to a single-pixel photodetector (or an array of relatively few photodetectors). Concentration of received light can be performed by curved concentrator such as a continuously-curved or faceted reflector. A portion or an entirety of the detector might be blinded (e.g., desensitized) by bright interferers such as the sun. An electro-optic shutter such as a liquid crystal (LC) structure can be used to selectively transmit or mask-off portions of the received light. For example, an LC structure can have regions of selectable opacity for a specified polarization of incident light. The LC structure can be controlled to render certain region opaque, such as to suppress interference from unwanted interferers such as the sun, bright lights, or unwanted reflections. An LC structure can also be used to implement a scanned transmit/receive technique.

Optical system for determining interferer locus among two or more regions of a transmissive liquid crystal structure

Embodiments of the present disclosure provide mechanisms for measuring currents flowing in one or more conductor wires. The mechanisms are based on using magnetic sensor pairs arranged within a housing with an opening for the wires, where each magnetic sensor pair can generate a pair of signals indicative of magnetic fields in two different directions. The outputs of the sensor pairs can be used to derive a measure of current(s) flowing through the one or more wires. The use of magnetic sensor pairs that can measure magnetic field in two different directions may enable simultaneous current measurement in multiple wires placed within the opening, improve accuracy of current measurements while relaxing requirements for precise control of the placement of the wire(s), reduce the impact of stray magnetic interference, and enable both AC and DC measurements.

Current measurement using magnetic sensors and contour intervals

Present disclosure describes an improved scaling mechanism for a multi-stage fixed-point FFT algorithm used to process signals received by radar or sonar systems. Proposed scaling includes scaling an output of every pair of consecutive butterfly stages of the FFT algorithm by a scaling factor equal to two times of the inverse of a growth factor for the pair of consecutive butterfly stages for the FFT algorithm for a purely complex exponential input signal. Besides this scaling, input signals are allowed to overflow by saturation. Such mechanism yields adequate performance of radar and sonar receivers implementing fixed-point FFTs for any types of input signals, from random to substantially complex exponential or sinusoidal signals. Proposed scaling achieves a balance between having signal to noise ratio (SNR) that is possible to obtain for a particular input signal and SNR that is needed to successfully process that signal for radar and sonar applications.

Scaling fixed-point fast Fourier transforms in radar and sonar applications

A method for generating a Fast Fourier Transform (FFT) is disclosed. The method includes providing an input signal to two or more fixed-point FFT algorithms that apply different scaling to reduce growth of their output, resulting in each of the FFT algorithms yielding an array of FFT output values characterized by a different gain. The method further includes determining, on a per-FFT output value basis, whether an output value of an FFT algorithm with a relatively high gain was clipped due to saturation. If not, then the output value of that FFT algorithm is included in the final FFT. Otherwise, an output value of an FFT algorithm with a lower gain is included in the final FFT. Reconstructing the final FFT by such combination of values from different FFTs allows benefiting from the advantages of both higher- and lower-gain FFTs while avoiding or minimizing their disadvantages.

Fixed-point high dynamic range fast fourier transforms

In an example, there is disclosed a digital signal processor having a register containing a modular integer configured for use as a thread offset counter. In a multi-stage, pipelined loop, which may be implemented in microcode, the main body of the loop has only one repeating stage. On each stage, the operation executed by each thread of the single repeating stage is identified by the sum of a fixed integer and the thread offset counter. After each pass through the loop, the thread offset counter is incremented, thus maintaining pipelined operation of the single repeating stage.

Thread offset counter

According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Predicate counter

A pipelined video pre-processor includes a plurality of configurable image-processing modules. The modules may be configured using direct processor control, DMA access, or both. A block-control list, accessible via DMA, facilitates configuration of the modules in a manner similar to direct processor control. Parameters in the modules may be updated on a frame-by-frame basis.

Dual control of a dynamically reconfigurable pipelined pre-processor

The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect network architecture that interconnects the compute array to the memory. In an example, the memory interconnect network architecture includes a switch-based interconnect network and a non-switch based interconnect network. The processor is configured to synchronously load a first data operand to each of the processing elements via the switch-based interconnect network and a second data operand to each of the processing elements via the non-switch-based interconnect network.

Memory interconnect network architecture for vector processor

Certain example embodiments of the present disclosure can provide a parallelized atomic increment. A vgather instruction returns to a plurality of processing elements the value of a memory location. A vgather_hit instruction returns to a function of the number of 'hits' to the memory location. In one embodiment, the function is unity. In another embodiment, the function is the number of hits having an ordinal designation less than or equal to the processing element receiving the return value.

Parallel atomic increment

An FFT operation is performed by dividing n time-domain input points into a plurality of groups of m points, performing a plurality of constant-geometry butterfly operations on each of the groups of m points, and finally performing at least one in-place butterfly operation on the group of n points.

FFT accelerator

The sampling rate of a digital signal is reduced by storing a series of partial sums of the digital signal instead of the signal itself, thus reducing the memory size required to perform the sampling-rate reduction.

Downsampling with partial-sum re-use

Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Methods and apparatus for image processing at pixel rate

Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

A hardware accelerator operable in an FFT mode and an FIR mode. The hardware accelerator takes input data and coefficient data and performs the calculations for the selected mode. In the FFT mode, a rate-two FFT is calculated, producing four real outputs corresponding to two complex numbers. In the FIR mode, one real output is generated. The hardware accelerator may switch from FFT mode to FIR mode using three multiplexers. All FIR components may be utilized in FFT mode. Registers may be added to provide pipelining support. The hardware accelerator may support multiple numerical-representation systems.

Growing community of inventors

Sharon, MA, United States of America

Boris Lerner