Synopsys, Inc.

Boris Gommershtadt

Dmitry Korchemny

Daniel Geist

Ilya Kudryavtsev

Nathaniel Azuelos

Alexander Rabinovitch

Solaiman Rahim

Alexander John Wakefield

Yan Zucker

Leonid Alexander Broukhis

Florent Duru

Ionut Silviu Cirjan

Alex Potapov

Naphtali Yehoshua Sprei

Leonid Greenberg

Alexander Shot

Alexander Goltzman

Yaron Shkedi

Gabriel Gouvine

Srivatsan Raghavan

Lakshmi Narayana Koduri Hanumath Prasad

A method of testing a product using confidence estimates is provided. The method includes identifying a set of candidate tests and estimating a respective confidence score for each candidate test, the confidence scores reflecting a level of confidence that the corresponding candidate tests will pass or fail when being performed on the product, the estimating including determining the respective confidence scores in dependence upon at least one of (i) previously obtained test results, (ii) changes to the product since a previous estimation or regression test has been performed and (iii) information regarding a user. The method includes identifying a candidate test having a confidence score that is below a threshold, in response to the identification of the candidate test, performing the candidate test, and providing, to a user, results of the performing of the candidate test.

Regression testing based on overall confidence estimating

A method of detecting a timing violation between a first sequential element and a second sequential element in a circuit design being emulated in a hardware emulation system includes, in part, determining a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element, reconfiguring a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers, setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship, reprogramming the first and second clocks in accordance with the delay, and detecting a timing violation if a change in an output of the first flip-flop is not stored in the second flip-flop within the delay.

Detecting timing violations in emulation using field programmable gate array (FPGA) reprogramming

An emulation host system can configure a reprogrammable hardware emulation system to emulate an electronic circuit design. The emulation host system can analyze the electronic circuit design for electronic circuits that are repetitive. The emulation host system can partition the electronic circuits onto a single partition. The emulation host system can map the single partition onto a single programmable logic element (PLE) of the reprogrammable hardware emulation system. The emulation host system can configure the reprogrammable hardware emulation system to emulate the electronic circuits using the single PLE.

Combinatorial and sequential logic compaction in electronic circuit design emulation

The independent claims of this patent signify a concise description of embodiments. A method is provided for reducing a size of an emulation clock tree for a circuit design. The method comprises identifying a fan-in cone of an input of a sequential element of the circuit design; identifying one or more fan-in cone sequential elements which do not directly affect the input of the sequential element; and removing the one or more identified fan-in cone sequential elements of the fan-in cone from the emulation clock tree. This Abstract is not intended to limit the scope of the claims.

Method and system for emulation clock tree reduction

A power usage estimation system for a design emulated on a field programmable gate array (FPGA) comprising a periodic dump unit implementing statistical data sampling to generate a periodic dump without emulation stops and interactions with a host, and without affecting the emulation performance.

Dedicated reconfigurable IP for emulation-based power estimation

A search for a regular expression in a tree hierarchy, includes, in part, searching for a match to the regular expression in a first subtree defined by a first node name, recording information about the first subtree if there is no match, determining whether a second subtree defined by a second node name is identical to the first node, skipping search of the second subtree if the second subtree is determined to be identical and prefix equivalent, with respect to the regular expression, to the first subtree. The second subtree is determined to be prefix equivalent to the first subtree when for any string s, a first prefix defined by a concatenation of the first node name and the string s results in a match if and only if a second prefix defined by a concatenation of the second node name and the string s results in a match.

Speeding matching search of hierarchical name structures

Coverage event counters for hardware verification emulations are implemented as linear feedback shift register-based counters generating encoded counter values indicative of a detected number of coverage events. To decode those counter values, a counter algorithm utilized to generate the encoded counter value may continue to be iterated after counting is complete until reaching a defined pattern, while counting the number of iterations (K) necessary to reach the defined pattern. The resulting counter value having the defined pattern is correlated with a mapping table to identify a numerical value, and an ordinal counter value indicative of the number of coverage events is determined based on the identified numerical value, less K.

Efficient realization of coverage collection in emulation

A method for calculating switching interface activity format (SAIF) for a circuit design includes segregating the circuit design into a plurality of hardware look up tables (LUTs), inserting switching interface activity format (SAIF) counter logic, and inserting a multiplexer between the LUTs and the SAIF counter logic. The SAIF counter logic includes shadow logic, at least one counter, and memory. The method further includes (i) selecting a previously-unselected LUT by switching the multiplexer to the selected LUT, (ii) executing a test through the selected LUT and the SAIF counter logic to generate SAIF data for the LUT, (iii) storing the SAIF data for the selected LUT in the memory, and (iv) continuing with (i) through (iii) until each of the plurality of LUTs is selected. The method further involves merging the SAIF data from each selected LUT into a consolidated SAIF file with SAIF data for the circuit design.

Generating SAIF efficiently from hardware platforms

Forming a logic circuit design from a behavioral description language that includes N force and M release statements applied to a net disposed in the design, includes, in part, forming N multiplexers and a controller controlling the select terminals of the N multiplexers. Each multiplexer receives a force signal at its first input terminal. The output signal of the imultiplexer is supplied to a second input terminal of (i+1)multiplexer. A driver signal driving the net in the absence of the force statements is applied to a second input terminal of a first multiplexer. The controller asserts the select signal of the imultiplexer if the iforce condition is active, and unasserts the select signal of the imultiplexer if any one of a number of predefined conditions is satisfied.

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Mevaseret Zion, Israel

Boris Gommershtadt