Intel Corporation

Boris Ginzburg

Eliezer Weissmann

Ronny Ronen

Alon Naveh

Efraim Rotem

Solomon B Trainin

Konstantin Levit-Gurevich

Jing Zhu

Simon Rubanovich

Gad Shlomo Sheaffer

Nadav Shulman

Elmoustapha Ould-Ahmed-Vall

Robert Valentine

Emily H Qi

Michael Mishaeli

Camille Chen

Oren Kaidar

Avishay Sharaga

Scott D Hahn

Zeev Sperber

Amit Gradstein

Christian Maciocco

David A Koufaty

Ehud Cohen

Anil Aggarwal

Shmuel Levy

Benny Eitan

Koichi Yamada

Wei Ey Li

Dheeraj R Subbareddy

Eugene Gorbatov

Kristoffer Fleming

Guy M Therien

James B Crossland

Xingang Guo

Ganapati Srinivasa

Robert L Farrell

Ilya Osadchiy

Yoav Zach

Karthikeyan Karthik Vaithianathan

Yuval Bachrach

Esfir Natanzon

Gadi Haber

Marc Jalfon

Shlomo Avital

Eran Friedlander

Vladimir Kondratiev

Ayelet Alon

Moshe Maury Bach

Max Fudim

Igor Breger

Aya Elhanan

Yuval Yosef

Oleg Margulis

Nati Dinur

Rony Ross

Paolo L Narvaez

Avi Mendelson

Myron Hattig

Sridharan Sakthivelu

Gedon Rosner

Alexander Tolpin

Amit Barak

Karthikeyan Vaithianathan

Sharon Ben-Porat

Esfirush Natanzon

Aamer Jaleel

Izoslav Tchigevsky

Shay Waxman

Tong Li

Hisham Abu-Salah

Ziv Aviv

Gordon Chinn

Oded Koren

Kenzo Van Craeynest

Sharon Ben-Porath

Avi Mendleson

Moustapha Hagog

A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Aggregated page fault signaling and handling

Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.

Mechanism for saving and retrieving micro-architecture context

An apparatus is described having multiple cores, each core having: a) a CPU; b) an accelerator; and, c) a controller and a plurality of order buffers coupled between the CPU and the accelerator. Each of the order buffers is dedicated to a different one of the CPU's threads. Each one of the order buffers is to hold one or more requests issued to the accelerator from its corresponding thread. The controller is to control issuance of the order buffers' respective requests to the accelerator.

Mechanism for issuing requests to an accelerator from multiple threads

An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

Apparatus and method for accelerating operations in a processor which uses shared virtual memory

A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime monitors execution of a code block. The code block has been compiled to have a reserved space appended to one end of the code block. The reserved space includes a metadata block associated with the code block or an identifier of the metadata block. The hardware stores a micro-architectural context of the processor in the metadata block. The micro-architectural context includes performance data resulting from a first execution of the code block. The hardware reads the metadata block upon a second execution of the code block and tunes the second execution based on the performance data.

In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.

Migrating tasks between asymmetric computing elements of a multi-core processor

A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a micro-architectural state and an architectural state of a processor in a common buffer of a memory upon a context switch that suspends the execution of a process. The micro-architectural state contains performance data resulting from the execution of the process. A restore instruction is executed to retrieve the micro-architectural state and the architectural state from the common buffer upon a resumed execution of the process. Power management hardware then uses the micro-architectural state as an intermediate starting point for the resumed execution.

Extension of CPU context-state management for micro-architecture state

In one embodiment, a processor includes an accelerator, a decoder to decode a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction, and an execution unit to execute the first decoded instruction to, for a thread executing on the accelerator that is to be placed in an inactive state, cause a save of context information for the thread, and a save of a vector identifying the accelerator corresponding to the context information, and execute the second decoded instruction to read the vector to determine the accelerator to restore saved context information into for the thread, read the saved context information, and restore the saved context information into the accelerator.

Context switching mechanism for a processor having a general purpose core and a tightly coupled accelerator

Aggregated page fault signaling and handline

A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.

CPU/GPU synchronization mechanism

A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing unit (GPU). The non-CPU may support virtual to physical address mapping and may thus be aware of the memory pages, which may not be pinned but may be accessed by the non-CPU. The non-CPU may notify or send such information to a run-time component such as a device driver associated with the CPU. The device driver may, dynamically, perform pinning of such memory pages, which may be accessed by the non-CPU. The device driver may even unpin the memory pages, which may be no longer accessed by the non-CPU. Such an approach may allow the memory pages, which may be no longer accessed by the non-CPU to be available for allocation to the other CPUs and/or non-CPUs.

Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform

A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a 2-D image stored in a memory coupled to the processor. The 2-D cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a 2-D structure of the 2-D image.

2-D gather instruction and a 2-D cache

Growing community of inventors

Haifa, Israel

Boris Ginzburg