Qualcomm Incorporated

Boris Andreev

Yong Xu

Farrukh Aquil

Lew G Chua-Eoan

Thomas R Toms

Chunlei Shi

Vinod Chamarty

Justin Joseph Rosen Gagne

Vikas Mahendiyan

Stephen A Molloy

Mikhail Popovich

Jeffrey Gemar

Tauseef Kazi

Aravind Bhaskara

Olivier Alavoine

Simon Booth

Edoardo Regini

Tao Shen

Renatas Jakushokas

Wenbiao Wang

Sejoong Lee

Saurabh Patodia

Ravindra Arvind Khedkar

Seong-Ook Jung

Xiaohua Kong

Nan Chen

Paul Bassett

Zhiqin Chen

Martin Saint-Laurent

Jeffrey Mark Hinrichs

Reza Jalilizeinali

Christopher Cooper Riddle

Junmou Zhang

Mukund Narasimhan

Patrick Isakanian

Haw-Jing Lo

Michael Hawjing Lo

Michael Drop

Chang Ki Kwon

Edwin Jose

Satish Krishnamoorthy

Sean Sweeney

Michael Thomas Fertsch

Trang Nguyen

Anand Meruva

Joon Young Park

Mayank Gupta

Xin Kang

Zeeshan Shafaq Syed

Amirali Shayan

Yuan-Cheng Pan

Christopher Phan

Mauricio Calle

IK-Joon Chang

Lew G Choa-Eoan

Arun David Arul Diraviyam

Yuxin Li

Murali Krishna Ade

Vishal Mishra

Yuan-Cheng Christopher Pan

Christopher C c/o Qualcomm Incorporated Riddle

In some aspects, an electronic device may receive a clock signal having a first frequency. The electronic device may receive, for a chip select training operation, a chip select signal having a pattern including high pulses and low pulses. The electronic device may perform, for a sampling window, the chip select training operation using the clock signal and the chip select signal, wherein the sampling window includes a quantity of pulses of the chip select signal. The electronic device may provide, via a first data in or out (DQ) pin, an indication of a first result of the chip select training operation for the high pulses of the chip select signal. The electronic device may provide, via a second DQ pin, an indication of a second result of the chip select training operation for the low pulses of the chip select signal. Numerous other aspects are described.

Enhanced chip select signal training

A memory interface circuit includes a first receiver coupled to a differential data strobe signal and a second receiver that has a first input coupled to a reference voltage source and a second input coupled to one of the pair of complementary signals. A qualification circuit is configured to detect a preamble transmission in the differential data strobe signal based on timing provided by an output of the first receiver when the memory interface circuit is in a first operating state, detect the preamble transmission in the differential data strobe signal based on timing provided by an output of the second receiver when the memory interface circuit is in a second operating state, and assert a preamble detection signal when the preamble transmission is detected. A gating circuit is configured to provide a receive clock signal when the preamble detection signal is asserted.

Read data capture for a high-speed double data rate interface

A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

Clock qualifier enhancement for external double data rate memory interfaces

Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.

Aging mitigation

A method for clock switching includes propagating a first clock signal through a first clock path, propagating a second clock signal through a second clock path, generating a first delay control signal based on the first clock signal, and generating a second delay control signal based on the second clock signal. The method also includes, in a first mode, coupling the first clock path to a delay circuit and inputting the first delay control signal to a control input of the delay circuit. The method also includes, in a second mode, coupling the second clock path to the delay circuit and inputting the second delay control signal to the control input of the delay circuit.

DDR phy parallel clock paths architecture

Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

Forced idling of memory subsystems

Micro-idle power in a subsystem of a portable computing device may be actively managed based on client voting. Each client vote may include a client activity status indication and a client latency tolerance indication. Votes are aggregated to provide an aggregate client latency tolerance, which may be used to obtain a set of micro-idle time values. Micro-idle timers in the subsystem may be set to associated micro-idle time values. The micro-idle timers determine whether one or more of the micro-idle time values have elapsed. A power management policy associated with each micro-idle time value determined to have elapsed may be applied to a portion of the subsystem.

Active power management in a computing device subsystem based on micro-idle duration

A method and an apparatus are provided. The apparatus is a hardware module that controls a power mode of a plurality of modules. The apparatus receives an indication of a desired operational frequency. Based on the received indication, the apparatus determines to switch from a first power mode associated with a first set of modules to a second power mode corresponding to the desired operational frequency and associated with a second set of modules. The apparatus enables modules in the second set of modules that are unassociated with the first power mode, stops traffic through the plurality of modules upon expiration of a time period after enabling the modules in the second set of modules that are unassociated with the first power mode, routes traffic through the second set of modules, and disables modules in the first set of modules that are unassociated with the second power mode.

Frequency power manager

A block power switch may be embedded with electrostatic discharge (ESD) protection circuitry. A transistor portion of the block power switch may be allocated to act as part of ESD protection circuitry and may be combined with an RC clamp to provide ESD protection. Adaptive body biasing (ABB) may be applied to the block power switch to reduce on-chip area and decrease leakage current of the block power switch.

Block power switch with embedded electrostatic discharge (ESD) protection and adaptive body biasing

An on-chip sensor measures dynamic power supply noise, such as voltage droop, on a semiconductor chip. In-situ logic is employed, which is sensitive to noise present on the power supply of functional logic of the chip. Exemplary functional logic includes a microprocessor, adder, and/or other functional logic of the chip. The in-situ logic performs some operation, and the amount of time required for performing that operation (i.e., the operational delay) is sensitive to noise present on the power supply. Thus, by evaluating the operational delay of the in-situ logic, the amount of noise present on the power supply can be measured.

On-chip sensor for measuring dynamic power supply noise of the semiconductor chip

In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first package-substrate connection, a second package-substrate connection, and metallization coupling the first package-substrate connection to the second package-substrate connection. The substrate is coupled to the package via the first package-substrate connection and the second package-substrate connection. The substrate includes a plurality of power domains and a power control unit. The second package-substrate connection of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first package-substrate connection of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package.

System and method of silicon switched power delivery using a package

In one particular embodiment, an integrated circuit includes a package and a substrate electrically and physically coupled to the package. The package includes a first pin, a second pin, and metallization coupling the first pin to the second pin. The substrate is coupled to the package via the first pin and the second pin. The substrate includes a plurality of power domains and a power control unit. The second pin of the package is coupled to a particular power domain of the plurality of power domains. The power control unit includes logic and a switch, where the switch includes a first terminal coupled to a voltage supply terminal, a control terminal coupled to the logic, and a second terminal coupled to the first pin of the package. The logic selectively activates the switch to distribute power to the particular power domain via the metallization of the package.

In an embodiment, a method is disclosed that includes receiving a clock signal at a delay chain of a circuit device and determining a value of the clock signal at a selected point within the delay chain. The method also includes adjusting the selected point when the value does not indicate detection of an edge of the clock signal.

Circuit device and method of measuring clock jitter

A device is disclosed that includes a first pin to supply power to a first power domain of an integrated circuit, a second pin to supply power to a second power domain of the integrated circuit, a switching regulator and a controller. The switching regulator is coupled to the first pin to provide a first regulated power supply to the first power domain and is coupled to the second pin to provide a second regulated power supply to the second power domain. The controller is coupled to the first pin and to the second pin to selectively reduce current flow to at least the second pin during a low power event.

System and method of power distribution control of an integrated circuit

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San Diego, CA, United States of America

Boris Andreev