Elbrus International Limited

Institut Tochnoi Mekhaniki I Vychislitelnoi Tekhniki Imeni S.a. Lebedeva

Boris A Babaian

Yuli Kh Sakhin

Feodor A Gruzdov

Vladimir Y Volkonsky

Leonid N Nazarov

Sergey K Okunev

Sergey A Rozhkov

Mikhail L Chudakov

Vladimir V Tikhorsky

Valeri G Gorokhov

Vladimir Yu Volkonskiy

Vladimir Yu Volkonski

Roman A Khvatov

Andrew V Yakushev

Valery Y Gorshtein

Alexander V Ermolovich

Alexey P Lizorkin

Vladimir V Rudometov

Oleg Alexandrovich Konopleff

Andrey Alexe'evich Vechtomov

Vladimir M Gushchin

Alexander M Artymov

Evgeny Z Stolyarsky

July K Sakhin

Alexandr K Kim

Vladimir J Volkonsky

Valdimir Y Volkonsky

Sergei V Semenikhin

Sergey Y Petrovsky

Vladimir S Volin

A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register files and access to their store addresses and data. Each explicit parallelism architecture processor of this system has an interprocessor interface providing the synchronization signals exchange, data exchange at the register file level and access to store addresses and data of other processors. The single-chip multiprocessor system uses ILP to increase the performance. Synchronization of the streams parallel execution is ensured using special operations setting a sequence of streams and stream fragments execution prescribed by the program algorithm.

Single-chip multiprocessor with clock cycle-precise program scheduling of parallel execution

Single-chip multiprocessor with cycle-precise program scheduling of parallel execution

A plurality of virtual memory spaces is implemented in a computer system designed to be binary-compatible with one or a plurality of foreign architectures. A single primary virtual memory space, designated as the native VM space, contains native codes directly executable by the host microprocessor, such as the binary translated codes and the binary translation process/system itself. One or a plurality of secondary virtual memory spaces, designated as the foreign VM space(s), contain foreign data and codes (to be translated into binary translated codes in the primary VM space) only, hence encompassing no native code executable by the host microprocessor directly. In one embodiment, each foreign architecture supported by the host microprocessor through the binary translation process is provided its own secondary VM space; hence the number of the secondary VM spaces supported equals the number of the foreign architectures supported. While all VM spaces are directly supported by the host microprocessor MMU hardware including, for example, corresponding address translation schemes and exception delivery, their properties may differ significantly, allowing for the primary VM to exploit the host microprocessor architecture benefits to the fullest possible extent at the same time as the secondary VM spaces mimic VM spaces of the corresponding foreign microprocessor architectures. After corresponding address translation, addresses from both the primary and the secondary VM space(s) are mapped to a single physical address space of the host microprocessor.

Method of using a plurality of virtual memory spaces for providing efficient binary compatibility between a plurality of source architectures and a single target architecture

Precise exceptions handling in the optimized binary translated code is achieved by transitioning execution to the non-optimized step-by-step foreign code execution means in accordance with one of the several coherent foreign states designated during the optimized translation of the foreign code. A method to improve the operation by avoiding complete foreign state updates in the optimized code, an apparatus to track the switching between the states and a method to recompute the complete foreign state in accordance to the current state identification, execution context and additional documentation provided during the translation time are proposed.

Method and apparatus for preserving precise exceptions in binary translated code

A method and apparatus for solving the output dependence problem in an explicit parallelism architecture microprocessor with consideration for implementation of the precise exception. In case of an output dependence hazard, the issue into bypass of a result of the earlier issued operation having an output hazard is cancelled. Latencies of short instructions are aligned by including additional stages on the way of writing the results into the register file in shorter executive units, which allows to save the issue order while writing the results into the register file. For long and unpredictable latencies of the instructions, writing of the result of the earlier issued operation having an output dependence hazard into the register file is cancelled after checking for no precise exception condition. All additional stages are connected to the bypass not to increase the result access time in case of this result use in the following operations.

Method for prioritizing operations within a pipelined microprocessor based upon required results

The present invention increases efficiency of a binary translation process by correlating selected foreign code to previously translated binary host code. This approach eliminates repetitive translation of foreign code when the foreign code is executed on a host computer system. During the translation process, a database of translated foreign code is populated and thereafter a software layer checks for correspondence between the foreign code and binary code stored in the database. If the database contains corresponding code, that code is transferred to system memory for execution and there is no need to retranslate the foreign code. Minimizing the time spent translating the foreign code results in improved execution speed on the host computer system. The software layer creates an index into the database by hashing the foreign code or by using the storage location of the foreign code. By way of example, the sector of a disk drive where the foreign code is stored determines the index into the database.

Method for fast execution of translated binary code utilizing database cache for low-level code correspondence

The present invention relates to a computer system adapted to efficiently execute binary translated code. In accordance with the present invention, foreign code is stored in a foreign virtual memory space, translated to acquire binary translated code, which is stored in a host virtual memory space and then executed. The host computer system isolates each virtual memory configuration into separate processes referred to as a virtual machine while enabling multiple virtual machines to exist simultaneously. Execution may switch from one virtual machine to another merely by switching to a new page table, where each page table describes the memory configuration of a virtual machine. Common system level resources are shared by the virtual machines under the control of a virtual memory manager.

Method for emulating hardware features of a foreign architecture in a host operating system environment

A method, implemented in a compiler, of balancing the workload between blocks in a control flow to reduce the overall execution time of control block includes steps for identifying &ldquo;hard&rdquo; blocks the consume excess resources, selecting hard block to unload, and unloading critical operations from a hard block to a control flow predecessor.

Critical path optimization&mdash;unload hard extended scalar block

A method and apparatus for optimizing scheduling of a block of program instructions to remove a condition resolving instruction from the critical path where the resolution of a condition controls the selection between input results, generated by predecessor operations, by a merge operation which passes the selected result to a successor operation. In a preferred embodiment, the successor operation is &ldquo;unzipped&rdquo; by duplicating the successor operations, providing predecessor results directly to the, duplicated successor operations, and scheduling the duplicated successor operations prior to the merge.

Critical path optimization-unzipping

A method and system for preparing branch instruction of a computer program, for compiling and execution in a computer system, in which each transfer instruction is split into two instructions: a control transfer preparation instruction and a control transfer instruction, wherein the control transfer preparation instruction contains the transfer address and is placed by the compiler several instructions ahead of the control transfer instruction, so that the number of clock cycles in the pipeline between transfer condition generation and transfer itself would be reduced.

Branch preparation

A method and computer apparatus are presented for providing a secure data architecture for computer memory of a processor. The apparatus comprises a memory unit and a processing unit. Data are stored in the memory unit and manipulated by the processing unit, which is programmed to implement the data architecture. Tagged single data words are formed by concatenating a tag to each of the single data words. Each of the tags takes a value that corresponds to the data type of the single data word to which it is concatenated. A data multiword is creating by concatenating tagged single data words having the same data type. The data multiword is stored within a location in the computer memory, the location selected to ensure alignment of the data multiword in accordance with its length. An effective tag value is constructed for the data multiword by concatenating all of its single word tags. An operation is prevented from being performed on the data multiword if the effective tag value is not one of a predetermined list of valid effective tag values for the operation.

Integrity of tagged data

A compiler optimization method for optimizing a scheduled block of instructions inserts a conditional branch instruction in place of a merge instruction to select between alternative paths when a condition is resolved.

Critical path optimization-optimizing branch operation insertion

A method, implemented by a compiler, for removing a store-load dependency from a critical path utilizes a compare address operation to determine at run time whether dependency actual exists. The operand to be stored is held in a temporary register and provided directly to the operations, using load operation result, in dependence on the value of the compare address operation result, so that the dependency is removed.

Method for removing dependent store-load pair from critical path

The present invention decreases the delay associated with loading an array from memory by employing an asynchronous array preload unit. The asynchronous array preload unit provides continuous preliminary loading of data arrays located in a memory subsystem into a prefetch buffer. Array loading is performed asynchronously with respect to execution of the main program.

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Moscow, Russia

Boris A Babaian