Taiwan Semiconductor Manufacturing Comp. Ltd.

Bor-Rung Su

Tsung-Shu Lin

Ming-Da Cheng

Wen-Hsiung Lu

Chang-Chia Huang

Hao-Yi Tsai

Tin-Hao Kuo

Po-Yuan Teng

Tzung-Hui Lee

Tai-Min Chang

De-Yuan Lu

Ming-Chih Yew

Chun-Hung Lin

Shih-Wei Liang

Yu-Chia Lai

Wei-Ting Lin

Yu-Chih Liu

Hsien-Ming Tu

Wen-Yi Lin

Chang-Pin Huang

Chien-Chia Chiu

Jing Ruei Lu

A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

Semiconductor package and manufacturing method thereof

The present disclosure relates a method of forming an integrated chip packaging device. In some embodiments, the method may be performed by forming a conductive trace on a surface of a packaging component. The conductive trace has an angled surface defining an undercut. A molding material is deposited over an entirety of the conductive trace and within the undercut. The molding material is removed from an upper surface of the conductive trace. The molding material has a sloped outermost sidewall after removing the molding material from the upper surface. A solder region is formed on the upper surface of the conductive trace.

Packaging device and method of making the same

The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is arranged on a surface of the first package component. The metal trace has an undercut. A molding material fills the undercut of the metal trace and has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component. A solder region is arranged over the metal trace.

A ring structure for chip packaging comprises a frame portion adaptable to bond to a substrate and at least one corner portion. The frame portion surrounds a semiconductor chip and defines an inside opening, and the inside opening exposes a portion of a surface of the substrate. The at least one corner portion extends from a corner of the frame portion toward the chip, and the corner portion is free of a sharp corner.

Ring structure for chip packaging

Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a first post-passivation interconnect (PPI) layer. The first PPI layer includes a landing pad and a shadow pad material proximate the landing pad. A polymer layer is over the first PPI layer, and a second PPI layer is over the polymer layer. The second PPI layer includes a PPI pad. The PPI pad is coupled to the landing pad by a via in the polymer layer. The shadow pad material is proximate the PPI pad and comprises a greater dimension than a dimension of the PPI pad. The shadow pad material is disposed laterally around the PPI pad.

Shadow pad for post-passivation interconnect structures

A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface of the metal trace.

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Taipei, Taiwan

Bor-Rung Su