National Science Council

Bor-Long Bai

Jar-Ferr Yang

A processor is provided for transforming N.times.N discrete cosine transform (DCT) coefficients F.sub.uv inputted from a run-length-code 5 (RLC) decoder and arranged in an input order into an image data f.sub.jk in an integrated circuit through a 2-D inverse discrete cosine transform (IDCT) procedure wherein subscripts u and v of DCT coefficients F.sub.uv are input frequency indices respectively having least significant bits (LSB) u.sub.0 and v.sub.0 having an exclusive-OR (XOR) and subscripts j and k of image data f.sub.jk are spatial indices generated by the integrated circuit, which comprises a cosine pre-multiplier array for computing cosine-weighted DCT coefficients, a principal subkernel mapper utilizing the cosine-weighted DCT coefficients by first referring to the indices u and v for forming a principal N/2.times.N/2 subkernel-weighted matrix F.sub.uv C.sub.1.sup.uv, an N.times.N accumulating matrix operating with the principal N/2.times.N/2 subkernel-weighted matrix F.sub.uv C.sub.1.sup.uv for progressively accumulating the image data f.sub.jk, and an output buffer for loading the image data f.sub.jk from the N.times.N accumulating matrix and transferring the image data f.sub.jk. Such a processor will reduce the number of the multipliers involved and simplify the hardware complexity therefor, fasten the pixel rate thereof so that the present method is especially suitable for the future HDTV systems, be able to progressively transform the arbitrary input order of DCT coefficients thereof so that the present method is especially suitable for the HDTV recording player systems and has an excellent regularity thereof and applies a simple hardware architecture so that the cost for the hardware is relatively low and the method is suitable for the manufacturing of VLSI for the HDTV systems.

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Taichung, Taiwan

Bor-Long Bai