Industrial Technology Research Institute

Bor-Chuan Kuo

Cheun-Song Lin

Rong-Chung Chen

Chih-Yuan Liu

Lie-Der Lin

Shu-Wei Wang

Wen-Jann Yang

Wen-jann Yang

A host computer, a graphics processor which receives and executes commands generated by the host computer, a display memory for storing display data, and a display device for displaying the display data are provided. A graphics context is also provided in which the parameters of a current image are stored. A processing unit for receiving and executing the graphics commands issued by the host computer and for converting the parameters stored in the graphics context into the display data, and a drawing unit for storing the display data in the display memory are also provided. Furthermore, a shared memory is provided which is directly accessible to the host computer so that it can write the parameters of a next graphics command into the shared memory while the graphics processor is executing a current command. The shared memory is also directly accessible to the graphics processor so that it can receive the parameters of the next graphics command to be executed directly from the shared memory. In a preferred embodiment, transfers of the graphics parameters between the graphics context and the shared memory are accomplished by employing a bit-block transfer method and a mask register stored in the graphics context.

Fast graphics control system capable of simultaneously storing and

A video display system includes a frame buffer comprising five sets of one or more VRAMs. An address generator for generating address locations in the frame buffer generates chip select, row select and column select address signals. Because the frame buffer comprises five sets of VRAMs, the generation of the address signals requires divide-by-five operations to be carried out. Accordingly, the address generator includes a unique divide-by-five circuit wherein the division is carried out by a sequence of additions and multiplications. In comparison to conventional systems, the video system of the present invention makes more efficient use of memory capacity in the frame buffer.

Memory architecture with graphics generator including a divide by five

A raster video display system utilizes memory capacity more efficiently than conventional raster display systems and is independent of the specific resolution of the screen which is utilized in the system. The raster display system comprises a VRAM with split transfer capability and a unique address generator which can determine when pixels from a particular row of the screen display start on one row of the VRAM and extend over to the next row of the VRAM.

Resolution independent raster display system

A pixel arrangement scheme for a high resolution graphics display system, using video RAMs. Pixels are time multiplexed instead of using a temporary memory in a conventional system. Memory arrangement to implement this scheme is made to obtain higher speed and lower cost, consistent with the increased capacity of VRAMs.

High resolution graphic display organization

A video display system includes a frame buffer includes five sets of one or more video random access memories. An address generator for generating address locations in the frame buffer generates ship select, row select and column select address signals. Because the frame buffer comprises five sets of video random access memories, the generation of the address signals requires divide-by-five operations to be carried out. Accordingly, the address generator includes a unique divide-by-five circuit wherein the division is carried out by a sequence of additions and multiplications. In comparison to conventional systems, the video system of the present invention makes more efficient use of memeory capacity in the frame buffer.

Growing community of inventors

Hsinchu, Taiwan

Bor-Chuan Kuo