Spansion Llc.

Advanced Micro Devices Corporation

Globalfoundries Inc.

Boon-Yong Ang

Simon S Chan

Inkuk Kang

Cinti Xiaohua Chen

Hajime Wada

Qi Xiang

Sameer S Haddad

Mark W Randolph

Hiroyuki Kinoshita

Hidehiko Shiraiwa

Jung-Suk Goo

Mehrdad Mahanpour

Harpreet Kaur Sachar

Mohammad Massoodi

Alice H Choi

According to one exemplary embodiment, a FET which is situated over a substrate, comprises a channel situated in the substrate. The FET further comprises a first gate dielectric situated over the channel, where the first gate dielectric has a first coefficient of thermal expansion. The FET further comprises a first gate electrode situated over the first gate dielectric, where the first gate electrode has a second coefficient of thermal expansion, and where the second coefficient of thermal expansion is different than the first coefficient of thermal expansion so as to cause an increase in carrier mobility in the FET. The second coefficient of thermal expansion may be greater that the first coefficient of thermal expansion, for example. The increase in carrier mobility may be caused by, for example, a tensile strain created in the channel.

Field effect transistor having increased carrier mobility

A method includes forming at least a portion of a semiconductor device in a processing chamber containing oxygen and removing substantially all of the oxygen from the processing chamber. The method further includes forming remaining portions of the semiconductor device in the processing chamber without the presence of oxygen.

Oxygen elimination for device processing

According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.

Bond pad structure for copper metallization having increased reliability and method for fabricating same

According to one exemplary embodiment, a method comprises a step of etching a trench in an ILD layer, said trench having sidewalls and a bottom surface. The method further comprises determining a height of the sidewalls of the trench. The method further comprises filling the trench with interconnect metal such the interconnect metal extends above the trench. According to this exemplary embodiment, the method further comprises performing a CMP process to remove a portion of the interconnect metal. In the present invention, the height of the sidewalls of the trench is utilized to control an amount of polishing performed in the CMP process. The remaining portion of interconnect metal in the trench forms an interconnect line, where the thickness of the interconnect line is controlled by utilizing the height of the sidewalls of the trench to control the amount of polishing in the CMP process.

Method for achieving increased control over interconnect line thickness across a wafer and between wafers

According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The structure further comprises a first interlayer dielectric layer situated over the at least one memory cell and over the substrate. The structure further comprises an oxide cap layer situated on the first interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises an etch stop layer comprising TCS nitride situated on the oxide cap layer, where the etch stop layer blocks UV radiation. The structure further comprises a second interlayer dielectric layer situated on the etch stop layer. The structure may further comprise a trench situated in the second interlayer dielectric layer and the etch stop layer, where the trench is filled with copper. The structure may further comprise an anti-reflective coating layer situated on the second interlayer dielectric layer.

Structure and method for protecting memory cells from UV radiation damage and UV radiation-induced charging during backend processing

A method and semiconductor device for detecting a heat generating failure in an unpassivated semiconductor device. The semiconductor device has an unpassivated surface and a heat generating failure, e.g., short circuit. A coating may be applied to the unpassivated surface of the semiconductor device. The coating may be non-electrically conducting and capable of localizing heat generated by the failure in a particular area. The semiconductor device may be biased. The failure may then be detected by detecting a location of the heat generated by the failure in the coating.

Detecting heat generating failures in unpassivated semiconductor devices

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Cupertino, CA, United States of America

Boon-Yong Ang