Other

Advanced Micro Devices Corporation

Boon Tang Teh

Takao Akaogi

Lee Edward Cleveland

Ali K Al-Shamma

Kendra Nguyen

Jin-Lien Lin

Yong K Kim

Edward V Bautista, Jr

Ken Cheong Cheah

Weng Fook Lee

Darlene G Hamilton

Colin Stewart Bill

Yong Bae Kim

Joseph Kucera

An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.

Address sequencer within BIST (Built-in-Self-Test) system

In a method and system for monitoring erase pulses applied on a sector of flash memory cells fabricated on a semiconductor substrate, a pulse counter and a pulse counter controller are fabricated on the semiconductor substrate. The pulse counter controller inputs a maximum number and outputs an indication of a sector fail if the flash memory cells of the sector do not pass erase verification with less than the maximum number of erase pulses applied on the sector during an erase verify BIST (Built-in-Self-Test) mode. In one example, the maximum number is a percentage of a diagonal total number of erase pulses needed to be applied on the sector until each flash memory cell at a diagonal location of the sector passes erase verification.

On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode

A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.

Memory line discharge before sensing

A voltage boost circuit ( ) for a flash memory ( ) includes a boosting circuit ( ), which is capable of boosting a portion of a power supply voltage (V ) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array ( ) of the memory. The voltage boost circuit further includes a balancing or clamping circuit ( ) for providing a nonzero adjustment voltage (V ) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.

Voltage boost level clamping circuit for a flash memory

A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits. The second decoding circuits are coupled to the first local driver circuits and supply a first boosted voltage to the first selected word line coupled to a first local driver circuit. The third decoding circuits are coupled to the second local driver circuits and supply a second boosted voltage to the second selected word line. The driving circuit supplies a series of boosted voltages to the first decoding circuits, the second decoding circuits, the third decoding circuits, the first local driver circuits, and the second local driver circuits.

Word line decoding architecture in a flash memory

A voltage boost circuit (,) for a memory (,) includes a boosting circuit (,) which is coupled to a boosted node (,) to boost a word line voltage for accessing a core cell of the memory. The voltage boost circuit further includes a reset circuit (,) coupled to the boosted node and including a switchable zero-threshold transistor (,) for resetting the boosted node to a reset voltage (VCC).

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Penang, Malaysia

Boon Tang Teh