Taiwan Semiconductor Manufacturing Comp. Ltd.

Boon-Khim Liew

Jian-Hsing Lee

Hung-Der Su

Yi-Hsu Wu

Jin-Yuan Lee

Mong-Song Liang

Jing-Meng Liu

Jyh-Haur Wang

A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p&minus; implanted region underlies the n&plus; region of the drain but does not underlie the n&plus; region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p&minus; implanted region underlies the n&plus; region of the drain but does not underlie the n&plus; region of the source.

CMOS output circuit with enhanced ESD protection using drain side implantation

The present invention provides a method of placing and routing metal wires for integrated circuit. In the method, a grid pattern is constructed by a plurality of floors with metal wires The grid size is set to be equal to a metal pitch. However, each via placed in the grid pattern has to be constrained by a checkerboard-like pattern. The checkerboard-like pattern consists of potential via sites and forbidden sites, wherein the potential via sites and the forbidden sites are intervened each other so that each potential via site in a comer of the grid has forbidden sites at its nearest neighbor corners. Furthermore, the connection cells is constructed and placed in a defined via site for connecting the metal wires in individually floor.

Place and route method for integrated circuit design

A method for fabricating a transistor device on a semiconductor substrate, comprising the following steps. A semiconductor substrate having a silicon surface with an overlying insulating dielectric layer is provided. The insulating dielectric layer is patterned to define hole/channel regions having predetermined widths. An amorphous silicon layer is formed having a predetermined thickness over the dielectric layer and the hole/channel regions, filling the hole/channel regions. Heating (grain growth) the amorphous silicon layer to form a planar silicon layer, comprising at least a portion of epitaxial-silicon, having a predetermined thickness, over the dielectric layer and through the hole/channel regions, filling the hole/channel regions. The planar silicon layer is patterned to expose the hole/channel regions and define transistor regions. Trenches are formed in the silicon surface adjacent the transistor regions. Shallow trench isolation regions are formed filling the trenches and having a predetermined depth. Transistor structures are formed within the transistor regions, separated by the shallow trench isolation regions.

Methods for formation of silicon-on-insulator (SOI) and source/drain-on-insulator(SDOI) transistors

A process for fabricating an I/O device, comprised with an LDD source/drain region, featuring a graded dopant profile, and simultaneously fabricating a core device, comprised with an LDD source/drain region, featuring a sharp dopant profile, has been developed. The process features the initial creation of the I/O device, LDD source/drain region, via an ion implantation procedure, followed by a furnace anneal procedure, to initiate transient enhanced diffusion, resulting in a graded dopant profile, for the I/O device, LDD source/drain region. The graded dopant profile, affords reduced risk of hot carrier effects, prevalent with the higher voltage, I/O devices. The creation of the core device, LDD source/drain region, is next addressed via another ion implantation, followed by a RTA procedure, used to activate the implanted species, and to create an LDD source/drain region, for the core device, featuring a sharp dopant profile, needed for performance objectives. The creation of insulator spacers, on the sides of the gate structures, is followed by the formation of heavily doped source/drain regions, for both I/O, and core devices.

Growing community of inventors

Hsinchu, Taiwan

Boon-Khim Liew