Altera Corporation

Boon-Jin Ang

Curt Wortman

Ali H Burney

Darren Van Wageningen

Dan Mansur

Thow-Pang Chong

Kerry S Veenstra

Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

Techniques for optimizing design of a hard intellectual property block for data transmission

A programmable logic configuration device is disclosed having a configuration memory accessible by a controller of the configuration device and by a second device. Arbitration circuitry is provided for arbitrating access to the configuration memory between the configuration controller and the second device.

Programmable logic configuration device with configuration memory accessible to a second device

Growing community of inventors

Penang, Malaysia

Boon-Jin Ang