Altera Corporation

Boon Jin Ang

Thow Pang Chong

Kar Keng Chua

Bee Yee Ng

Jun Pin Tan

Choong Kit Wong

Tat Mun Lui

Wei Yee Koay

Eng Huat Lee

Kim Pin Tan

Ie Chen Chia

Zun Yang Tan

Sammy S Cheung

Ket Chiew Sia

Chuan Khye Chai

Teik Wah Lim

Kok Yoong Foo

Chiang Wei Lee

Tze Swan Tan

Richard Jin Guan Saw

Want Sent Khor

Sergey Yuryevich Shumarayev

Chiakang Sung

Khai Nguyen

Kyung Suk Oh

Irfan Rahim

Hae-Chang Lee

Kerry S Veenstra

Tony K Ngai

Rafael Czernek Camarota

Henry Y Lui

Victor Maruri

Hee Kong Phoon

Surinder Singh

Kiun Kiet Jong

Guang Chen

Darren Van Wageningen

Chin Ghee Ch'ng

Eu Geen Chew

Foong Tek Chan

Xiabao Wang

Geok Sun Chong

Yan Jiong Boo

Yu Fong Tan

Guang Sheng Soh

Kam Fai Suit

Teng Kuan Koay

Sze Huey Soo

One embodiment relates to an integrated circuit which includes a method of dynamically adjusting a receive buffer in an integrated circuit. A fixed-size buffer circuit of the receive buffer is used to buffer data received by way of a serial interface circuit. The performance of the serial interface circuit are monitored. The receive buffer is dynamically extended based on said performance. Other embodiments, aspects, and features are also disclosed.

Integrated circuit with dynamically-adjustable buffer space for serial interface

A high speed IO buffer is disclosed. The high speed IO buffer includes a first P-type metal oxide semiconductor (PMOS) transistor coupled to an IO voltage source. The high speed IO buffer also includes a first N-type metal oxide semiconductor (NMOS) transistor coupled to a ground source, a second PMOS transistor coupled to the first PMOS transistor and a pad and a second NMOS transistor coupled to the first NMOS transistor and the pad. The first PMOS transistor, the first NMOS transistor, the second PMOS transistor and the second NMOS transistor are arranged in a cascoded arrangement.

High speed IO buffer

A system and a method of manufacture of an integrated circuit system includes: a supply grid connected to an active component of an integrated circuit die; a high voltage capacitor connected to the supply grid; a low voltage decoupling capacitor connected to the supply grid; a pass gate gating the low voltage decoupling capacitor; and a pass gate control for controlling the pass gate to cause the high voltage capacitor and the low voltage decoupling capacitor to stabilize voltage of the supply grid during activity of the active component.

Integrated circuit system with dynamic decoupling and method of manufacture thereof

A method for determining clock uncertainties is provided. The method includes identifying clock transfer types between registers from an integrated circuit design and identifying contributors to the clock uncertainties for each of the clock transfers. The jitter associated with each identified contributor is calculated for both set-up time and hold time. This calculated jitter is incorporated into a slack calculation to determine whether timing constraints are met for a circuit design.

Method and apparatus for determining clock uncertainties

Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The sleep circuit is operable to receive a control signal and further operable to place the memory circuit in different modes of operation. The memory circuit may be placed in either a first mode of operation, a second mode of operation or a third mode of operation based at least partly on the control signal. An input terminal of the sleep circuit is coupled to an output terminal of the control circuit. The control circuit is operable to receive an enable signal and is operable to supply the control signal to the sleep circuit at first, second and third voltage levels during the first, second and third modes of operation, respectively, based on the enable signal and a clock signal.

Memory circuitry with dynamic power control

Methods, computer program products, and systems are disclosed associated with calculating a routability metric for a second IC design using inputs from the compilation to a first IC design. The first and second IC designs are alternative implementation options for a user circuit design, such as FPGA and structured ASIC options. Information about user design demands on routing resources of one IC design are considered along with information about the projected supply of routing resources in another IC design, to produce a routing metric. The routing metric may be mapped to a degree of difficulty indicator, and either may be used to condition a compile of the user circuit to the second IC design or be used in other ways.

Predicting routability of integrated circuits

I/O circuits and a method for transmitting different types of I/O signals are disclosed. An embodiment of the I/O circuit comprises multiple transistors with multiple switches coupled to the transistors. The switches may be used to selectively couple the transistors to a power source or to another transistor to form different transistor configurations. The transistors may be configured to form a parallel configuration or a stacked configuration. Stacking up transistors may reduce voltage swings in the transistors and subsequently reduce degradation in the transistors.

Integrated circuit with configurable I/O transistor arrangement

Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block.

Frequency control clock tuning circuitry

Integrated circuits with error detection circuitry are provided. Integrated circuits may include memory cells organized into frames. The error detection circuitry may compress each frame to scan for soft errors. The error detection circuitry may include multiple input shift registers (MISRs), a data register, and a signature comparator. The data frames may be read, compressed, and shifted into the MISRs in parallel. After all the data frames have been read, the MISRs may provide a scanned MISR signature at their outputs. Computer-aided design (CAD) tools may be used to calculate a precomputed MISR signature. The precomputed MISR signature may be loaded into the data register. The signature comparator compares the scanned MISR signature with the precomputed MISR signature. If the signatures match, then the device is free of soft errors. If the signatures do not match, then at least one soft error exists.

Memory error detection circuitry

Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.

Multiplier with built-in accumulator

Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.

Configurable memory block

Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

Data encoding scheme to reduce sense current

A method of designing at IC is described. In one embodiment, the method includes providing an option to select a mask layer set from a plurality of mask layer sets, the plurality of mask layer sets including a first mask layer set and a second mask layer set, where the second mask layer set is an alternative mask layer option to the first mask layer set. In one embodiment, the method further includes receiving a selection from a user choosing a mask layer set from the plurality of mask layer sets. In one embodiment, the receiving occurs after design of the IC and prior to fabrication of the IC. Also, in one embodiment, the plurality of mask layer sets are predetermined mask layer sets. In one embodiment, the first mask layer set is a standard threshold voltage (SVT) mask layer set and the second mask layer set is a high threshold voltage (HVT) mask layer set. In one embodiment, core devices of the SVT mask layer set are SVT devices and some periphery devices of the SVT mask layer set are HVT devices. In one embodiment, hybrid cell (H-cell) devices of the HVT mask layer set are HVT devices and some periphery devices of the HVT mask layer set are HVT devices.

Method of designing integrated circuits including providing an option to select a mask layer set

Growing community of inventors

Butterworth, Malaysia

Boon Jin Ang