Altera Corporation

Intel Corporation

Boon Hong Oh

Chee Seng Tan

Chau Perng Chin

Chee Wai Yap

Jon Michael Harris

Vivek Gowri-Shankar

David Johnston

David Wheeler

Peter Schepers

Da Hai Tang

Yee Hui Lee

Ivan Fu Sun Teh

Chee Sent Tan

Laila Ahmed Saad Ahmed Ahmed

Yeong Liang Low

A method for an audiovisual receiver to request an audiovisual transmitter to reset a communication link includes requesting the reset when the audiovisual receiver determines that the communication link is unlocked. The communication is determined to be unlocked when the active geometry of successive audiovisual frames transmitted from the transmitter to the receiver is determined by the receiver to be inconsistent. The communication is also determined to be unlocked when the interval between control bits of the successive audiovisual frames is inconsistent. When one or both of the inconsistencies is determined, the receiver sets an error bit in a register of the receiver that is accessible by the transmitter to determine from the receiver that the communication link is unlocked.

Circuit and method for link verification by HDCP receiver

The disclosure relates to systems, methods and devices to provide race-condition true random number generator (TRNG) for soft intellectual property (IP) in field-programmable gate arrays (FPGAs). In an exemplary embodiment, a pair of long adder chains are raced against one another to complete a full cycle. Due to variances in the silicon, different chains will win each race at different times and thereby produce entropy. A calibration circuit can be used to set up the adder chains in an appropriate initial state to maximize the entropy produced. This structure has been found to be robust to layout changes, and the use of two such adder-chain-pairs reduces interference from other structures. Among others, the soft IP makes adding a robust TRNG to an FPGA much easier without concerns for how the structures are laid out or what other IP is nearby in the layout. The disclosed embodiments reduces the effort to add a TRNG to an FPGA design and improves the robustness of the TRNG making the design FIPS certifiable.

System, method and apparatus for race-condition true random number generator

A method for performing pattern detection and alignment on a programmable logic device is disclosed. A word aligner unit, implemented by a hard intellectual property block, is configured to detect a plurality of control characters by recognizing a proper subset of bits that are common among the plurality of control characters. It is determined whether a predetermined number of consecutive control characters has been detected in a frame of data. A boundary location associated with a detected predetermined number of consecutive control characters from the word aligner unit is identified. The frame of data is aligned in response to the boundary location associated with the detected predetermined number of consecutive control characters.

Method and apparatus for performing non-unique data pattern detection and alignment in a receiver implemented on a field programmable gate array

Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.

Multi-rate transceiver circuitry

Circuitry and methods of operation thereof for video communication are described herein. The circuitry described herein may be programmable circuitry. The circuitry may include a receiver circuit and/or a transmitter circuit and one of the provided techniques includes receiving and/or transmitting video data. The receiver circuit may include a detector circuit that is used to determine the data rate of the received video data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. The data rate of the video data stream may be associated with a video standard. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit. The circuitry discussed herein can support multiple protocol data paths.

Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include a receiver circuit and one of the provided techniques includes receiving a data stream at the receiver circuit. The receiver circuit may include a detector circuit that is used to determine the data rate of the received data stream. A controller block in the receiver circuit may accordingly configure a deserializer circuit in the receiver circuit based on the data rate of the received data stream. The circuitry may further include a transmitter circuit for transmitting data streams. The transmitter circuit may be configured during runtime based on the data rate of a data stream that is being transmitted. In some instances, irrespective of the data rate of the data stream being transmitted, a constant reference clock may be used in the transmitter circuit.

A deinterlacing apparatus includes a buffer to receive a plurality of consecutive fields of an interlaced video and a field combination module coupled to the buffer to deinterlace the interlaced video in accordance with cadence of the interlaced video. The deinterlacing apparatus also includes a cadence detection module to detect the cadence by (1) causing each of the fields to be combined with its preceding field into a frame and with its subsequent field into another frame to obtain a plurality of combined frames, (2) determining a comb factor of each of the combined frames to obtain a sequence of comb factors of the combined frames, and (3) determining if the sequence of comb factors of the combined frames follows a pre-determined repeating pattern. A cadence detection method is also described.

Method and apparatus for performing robust cadence detection in a video deinterlacer

A circuit includes a receiver circuit, a data valid monitor circuit, a clock signal generation circuit, and a phase shift circuit. The receiver circuit is operable to generate a first periodic signal, a sampled data signal based on an input data signal, and a data valid signal based on a predefined number of bits in the sampled data signal. The data valid monitor circuit is operable to generate a count value by counting periods of the first periodic signal. The data valid monitor circuit is operable to generate a phase error signal based on the data valid signal and the count value. The clock signal generation circuit is operable to generate a second periodic signal. The phase shift circuit is operable to generate a third periodic signal based on the second periodic signal and to adjust a phase of the third periodic signal based on the phase error signal.

Growing community of inventors

Bukit Mertajam, Malaysia

Boon Hong Oh