Pixart Imaging Incorporation

Boon-Eu Seow

Kei-Tee Tiew

Ping-Seng Lee

An SAR ADC includes: at least one sub-ADC, configured to convert a corresponding input signal to a corresponding SAR code; and a tuning control unit, configured to adjust a full-scale voltage (VFS) of each of the sub-ADC to a corresponding predetermined target level in a VFS tuning mode. The tuning control unit generates a tuning code to control an adjusting capacitor array coupled to the sub-ADC for tuning the VFS. The tuning control unit controls the sub-ADC to convert plural reference voltages in the VFS tuning mode and extrapolating the conversion result to determine a corresponding calibrating VFS. The tuning control unit determines whether the calibrating VFS meeting the target VFS and loops the adjusting process in a linear search method or in a SAR method.

SAR ADC capable of full-scale voltage auto-tuning and method for the same

A non-overlapping clock generator generating an in-phase output clock signal and a reversed-phase output clock signal which are non-overlapped with each other, includes: a first and a second XOR gates, a first and a second load transistors, which are cross coupled, and includes: a first and a second delay circuits. The first delay circuit is coupled between the in-phase output clock signal and a control terminal of the first load transistor. The second delay circuit is coupled between the reversed-phase output clock signal and a control terminal of the second load transistor. Each of the XOR gates includes at least one pass transistor logic circuit configured to execute XOR logic operation and coupled to a first control voltage. A non-overlapping period is determined according to the first control voltage and/or a first delay period of the first delay circuit and a second delay period of the second delay circuit.

Growing community of inventors

Penang, Malaysia

Boon-Eu Seow