Spansion Llc.

Advanced Micro Devices Corporation

Apple Inc.

Boon-Aik Ang

Derric J H Lewis

Nian Niles Yang

Dennis M Fischette, Jr

Meei-Ling Chiang

Yonggang Wu

Guowei Wang

Samed Maltabas

Fan Wan Lai

Steve Lim Choi

Soo-yong Park

Yu Cheng Chen

Yi Cheng

Michael Achter

Colin D Nayler

Harry Kuo

Shaobo Liu

Oikwan Tsang

Yu Chen

Dennis Lau

Hung Duy Vo

Chieu Yin Chia

Zhen-Hua Liu

Phil Keller

Litesh Sajnani

Hairong Yu

Gregory N Santos

Richard Y Su

Pyoungwon Park

A clock generator circuit may include a multiplex circuit and a phase-locked loop circuit. The multiplex circuit may generate a reference clock signal for the phase-locked loop circuit by selecting one of different clock signals. In response to a switch of the reference clock signal from one clock signal to another, the phase-locked loop circuit may disable phase-locking and enter into a frequency acquisition mode during which the frequency of the phase-locked loop circuit's output clock signal is adjusted based on the frequency of the newly selected reference clock signal. After a period of time has elapsed, the phase-locked loop circuit returns to phase-locking operation.

Reference clock switching in phase-locked loop circuits

A clock signal generated by a fractional-N phase-locked loop circuit may include deterministic jitter resulting from a sigma-delta modulation of a frequency divisor used by a divider circuit. In order to reduce such jitter, a cancelation circuit is employed that can generate a feedback signal by delaying an output signal from the divider circuit, where the amount of delay applied to the output signal is based on an accumulated phase residue from the modulation of the frequency divisor. The resultant feedback signal is compared to a reference signal, results of which are used to adjust an oscillator circuit generating the clock signal, thereby reducing the deterministic jitter.

Spur cancelation in phase-locked loops using a reconfigurable digital-to-time converter

A phase locked loop (PLL) system includes a PLL and a calibration circuit. The PLL has a reference clock input, a voltage controlled oscillator (VCO) clock output, and a feedback clock output. The calibration circuit provides a reference clock signal to the reference clock input of the PLL, induces first and second phase disturbances between the reference clock signal and a feedback clock signal, measures respective first and second zero crossing times of a phase error between the reference clock signal and the feedback clock signal, and estimates a bandwidth of the PLL in response to an average of the first and second zero crossing times.

Phase locked loop system with bandwidth measurement and calibration

In the present method of measuring the current of a first current source, the current thereof may be combined with either the current of a second current source, or the current of a third current source. Based on a combination of the current of the first current source and either (a) the current of the second current source or (b) the current of the third current source, a digital output is provided. If this digital output is of a first value, the state of combining the current of the first current source with the current of the second current source becomes in effect. If this digital output is of a second value, the state of combining the current of the first current source with the current of the second current source becomes in effect.

Method of measuring flash memory cell current

Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of the memory cell.

Table lookup voltage compensation for memory cells

A voltage regulator is provided. The voltage regulator provides an output voltage that is proportional to a digital multi-bit select signal. The voltage regulator includes a coarse voltage regulator and a fine voltage regulator. The coarse voltage regulator provides a coarse output voltage based on an output of a voltage divider selected based on the most significant bits of the select signal. The fine voltage regulator provides the output voltage from the coarse output voltage. The output of the fine voltage regulator is adjusted by adjusting the output of an adjustable current source that is provided to a resistor that is coupled between the output and one of the inputs of the fine voltage regulator.

Apparatus and method for generating wide-range regulated supply voltages for a flash memory

A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

Bitline voltage driver

A method and apparatus are provided for high performance, high voltage memory operations on selected memory cells () of a semiconductor memory device (). A high voltage generator () during program or erase operations provides a continuous high voltage level () on selected word lines () and maintains a continuous high voltage level supply to a bit line decoder () which sequentially provides the high voltage level () to a first portion of bit lines () and discharges () those bit lines () before providing the high voltage level to a second portion (). For additional improvements to program operations, the high voltage generator () decouples high voltages provided to the word lines () and the bit lines () by providing a current flow control device () therebetween and provides a boosting voltage at a time () to overcome a voltage level drop () resulting from a capacitor load associated with selected bit lines () and/or the bit line decoder () precharges () a second portion of the bit lines () while providing a high voltage level to a first portion to program () a first portion of memory cells (). For improvements to read operations, whether dynamic reference cells () are blank is determined by providing non-identically regulated high voltage levels from a first voltage source () to the dynamic reference cells () and from a second voltage source () to static reference cells () and, if the dynamic reference cells () are not blank, reads selected memory cells () by providing identically regulated high voltage levels to the selected memory cells (), the dynamic reference cells () and the static reference cells ().

Method and apparatus for high voltage operation for a high performance semiconductor memory device

A method and apparatus are provided for improved noise reduction from switching on and off drain pumps () in a high voltage generator. The drain pumps () are divided into groups () and activation of the groups () of drain pumps () is staggered (). In addition, when drain pumps are switched on and off for power conservation or to maintain a steady state high voltage level, the groups () of drain pumps () are switched on and off in response to various predetermined high voltage levels (), with different voltage levels for different groups () of drain pumps ().

Method and apparatus for drain pump operation

A pipeline ADC (Analog to Digital Converter) unit is provided that has a first and a second multi-stage portion. The first multi-stage portion has a first plurality of converter stages for converting a first analog signal to a first digital signal having a first digital resolution. The second portion has a second plurality of converter stages to convert a second analog signal to a second digital signal having a second digital resolution. The second plurality includes the first plurality. The pipeline ADC unit selectively uses either the first plurality of stages alone, or the second plurality. The pipeline ADC unit may be used in a WLAN (Wireless Local Area Network) communication device.

Variable accuracy pipeline ADC for WLAN communications devices

A physical layer transceiver of a home network station connected to a telephone medium has an architecture enabling adaptation of detection circuitry based on received network signals to enable reliable recovery of data signals. The physical layer transceiver includes an input amplifier that amplifies network signals according to one of 128 gain settings set by a receiver gain control signal. A signal conditioning circuit includes an envelope detector configured for outputting an envelope of the amplified received signal, and an energy detector configured for outputting an energy signal of the amplified received signals. The envelope signal and the energy signal are supplied to slicer threshold circuits, configured for outputting noise, peak, data event and energy event signals based on noise threshold, peak threshold, data transition threshold, and energy threshold signals, respectively. A digital controller controls the input amplifier gain and the threshold values, and adjusts the gain and threshold values based on the noise event signal and the peak event signal within an access ID (AID) interval. Hence, the receiver can be optimized on a per-packet basis for receiving network signals by adjusting the receiver portion during the AID preamble phase of the data packet. Gain control may also be used by the digital controller on the transmitter portion to selectively adjust the output gain for optimizing transmission to a destination home network station.

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Santa Clara, CA, United States of America

Boon-Aik Ang