Altera Corporation

Bonnie I Wang

Chiakang Sung

Joseph Huang

Khai Nguyen

Xiaobao Wang

Yan Chong

In Whan Kim

Philip Pan

Richard G Cliff

Tzung-Chin Chang

Wayne Yeung

Gopinath Rangan

Gopi Rangan

Francis B Heile

Bruce B Pedersen

David Wolk Mendel

Cameron R McClintock

Kerry S Veenstra

Srinivas T Reddy

Christopher F Lane

Phillip Pan

Henry Kim

Fung Fung Lee

Jeffrey Tyhach

Jonathan Chung

Thomas Henry White

Ninh D Ngo

John Henry Bui

Robert R N Bielby

Surgey Y Shumarayev

Weiqi Ding

Myron Wai Wong

Nitin Prasad

Michael H M Chu

Sanjay K Charagulla

Warren Nordyke

Jeffrey T Watt

Tim Tri Hoang

Gordon Raymond Chiu

Tony K Ngai

Yanzhong Xu

Hong Shi

Jun Liu

Zhe Li

Sean Shau-Tu Lu

Pradeep Nagarajan

Weizhong Xu

Richard Hernandez

Haidang Lin

Xiabao Wang

Bruce B Pendersen

Im Whan Kim

Khai Huang

A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that transmits a selection signal to a multiplexer. The multiplexer selects a level of the reference voltage based on the selection signal from the calibration control circuit.

On-die input reference voltage with self-calibrating duty cycle correction

Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Programmable high-speed I/O interface

An integrated circuit is disclosed. The integrated circuit includes an input-output (IO) buffer circuit. The IO buffer circuit further includes first and second transistors coupled in series. The first transistor receives an input signal and the second transistor receives a pulsed voltage signal. Furthermore, a method to operate the IO buffer circuit is also disclosed.

Input-output buffer circuit with a gate bias generator

An integrated circuit such as a programmable integrated circuit may include input-output circuits each having respective memory controller circuitry. The memory controller circuitry of the input-output circuits may be electrically coupled via a backbone path and configured to collectively form a memory controller. Each memory controller circuitry may include a protocol control circuit and input-output lanes. Memory access requests from on-chip circuitry may be provided to only a selected input-output circuit. The protocol control circuit of the selected input-output circuit may receive the memory access requests and generate memory control signals and local control signals from the memory access requests. The memory control signals may be provided to external memory. The local control signals may be provided to input-output circuits over the backbone path and synchronize the input-output circuits in conveying data between the integrated circuit and the external memory.

Integrated circuits having input-output circuits with dedicated memory controller circuitry

Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.

Multiple data rate interface architecture

An integrated such as a programmable integrated circuit may include input-output pins that have associated input-output circuits. An input-output circuit may include memory interface circuits, clock recovery interface circuits, shared interpolator circuitry, and selection circuitry that may be configured to convey control signals from selected interface circuits to the shared interpolator circuitry. The interpolator circuitry may receive multiple clock signals and perform phase interpolation operations on the clock signals based on the selected control signals to produce modified clock signals. The modified clock signals may be used by the selected interface circuits for communications over the input-output pins. Logic design computing equipment such as computing equipment having CAD tools may be used to configure the selection circuitry.

Input-output circuitry for integrated circuits

An integrated circuit in a multi-chip package is provided. The integrated circuit may include adjustable interface circuitry configured to interface with other off-chip components. In particular, the adjustable interface circuitry may include a microbump input-output buffer operable to drive signals off of the integrated circuit and operable to receive signals from other integrated circuits in the multi-chip package via a microbump. The microbump input-output buffer may include output buffers and input buffers. The output buffers may have programmable drive strengths and may each be selectively switched in and out of use depending on the desired application. Each output buffer may include a level shifter, a buffer circuit, and multiple inverter-like circuits each of which can be turned on or off to adjust the drive strength of that output buffer.

Adjustable drive strength input-output buffer circuitry

A voltage-mode differential driver is disclosed. The differential driver includes two driver arms, each driver arm including a variable-impedance driver for driving a single-ended output signal. Each variable-impedance driver comprises multiple driver slices, where each driver slice includes a pre-driver circuit and a driver circuit. Advantageously, it has been determined that the disclosed voltage-mode driver design requires less power than conventional current-mode drivers. In one implementation, the disclosed voltage-mode driver design provides the capability of independently programming the delay of the two single-ended outputs so as to compensate for differential skew. Other embodiments and features are also disclosed.

Programmable high-speed voltage-mode differential driver

Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

Dynamic termination-impedance control for bidirectional I/O pins

Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device.

Write-leveling implementation in programmable logic devices

Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.

Input-output circuit and method of improving input-output signals

One embodiment relates to a programmable output buffer which includes first and second programmable variable-impedance single-ended driver circuits and first and second termination circuits. The first termination circuit is coupled to a first output pin which is driven by the first programmable variable-impedance single-ended driver circuit, and the second termination circuit is coupled to a second output pin which is driven by the second programmable variable-impedance single-ended driver circuit. The first and second termination circuits are programmable to either provide parallel termination for a differential signal or drive single-ended signals with the parallel termination turned off. Other embodiments and features are also disclosed.

Programmable output buffer

Programmable high-speed interface

Growing community of inventors

Cupertino, CA, United States of America

Bonnie I Wang