Samsung Electronics Co., Ltd.

Bongyong Lee

Minkyung Bae

Myunghun Woo

Doohee Hwang

Taehun Kim

Junhee Lim

Tae Hun Kim

Dongchan Kim

Jaesung Sim

Moorym Choi

Ae-Jeong Lee

Taeyoung Kim

Kohji Kanamori

Jin-Young Kim

Jeehoon Han

Sang-Hoon Kim

Jaegoo Lee

Hyunmog Park

Sangyoun Jo

Hyojoon Ryu

Yukio Hayakawa

Euido Kim

Sang-Youl Kwon

Siyeon Cho

Haebum Lee

Houng-kuk Jang

Hye Yeon Yun

Heesuk Kim

A magnetic memory device includes a loop-type magnetic track having a first part and a second part that are arranged in a counterclockwise direction, a first conductive line on a top surface of the first part, and a second conductive line on a bottom surface of the second part. The magnetic track includes a lower magnetic layer, a spacer layer, and an upper magnetic layer that are sequentially stacked. Each of the first and second conductive lines includes heavy metal. Each of the first and second conductive lines is configured to generate spin-orbit torque caused by current that flows therein. The spin-orbit torque causes magnetic domains in the magnetic track to move in a clockwise direction or in the counterclockwise direction.

Magnetic memory device and method of operating the same

A semiconductor device includes a first structure and a second structure thereon. The first structure includes a substrate, circuit elements on the substrate, a lower interconnection structure electrically connected to the circuit elements, and lower bonding pads, which are electrically connected to the lower interconnection structure. The second structure includes a stack structure including: gate electrodes and interlayer insulating layers, which are alternately stacked and spaced apart in a vertical direction; a plate layer that extends on the stack structure; channel structures within the stack structure, separation regions, which penetrate at least partially through the stack structure, and upper bonding pads, which are electrically connected to the gate electrodes and the channel structures, and are bonded to corresponding ones of the lower bonding pads.

Semiconductor storage devices and data storage systems including the same

A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

Method of fabricating a vertical semiconductor device

Vertical semiconductor device and method of fabricating the same

A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.

Semiconductor devices having increased efficiency in generation of gate-induced drain leakage current without insulation deterioration and methods of operating the same

A three-dimensional semiconductor memory device may include a stack including gate electrodes sequentially stacked on a substrate and a vertical structure penetrating the stack. The vertical structure may include a vertical channel portion, a charge storing structure on an outer side surface of the vertical channel portion, and a pad. The pad may include a first pad portion disposed in an internal space surrounded by the vertical channel portion and a second pad portion provided on the first pad portion and extended onto a top surface of the charge storing structure. A portion of the first pad portion may be disposed at the same level as an uppermost electrode of the gate electrodes.

Three-dimensional semiconductor memory devices

A three-dimensional (3D) semiconductor memory device may include a stack structure including gate electrodes sequentially stacked on a substrate, and a vertical channel penetrating the stack structure. The gate electrodes may include a ground selection gate electrode, a cell gate electrode, a string selection gate electrode, and an erase gate electrode, which are sequentially stacked on the substrate.

Three-dimensional semiconductor memory devices and method of manufacturing the same

An operating method of a nonvolatile memory device which includes a cell string including a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method including: programming an erase control transistor of the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground selection transistor of the plurality of cell transistors and the common source line or between a string selection transistor of the plurality of cell transistors and the bit line.

Nonvolatile memory device, an operating method thereof, and a storage system including the nonvolatile memory device

A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.

A three-dimensional semiconductor memory device may include a substrate comprising a cell array region and a connection region, an electrode structure including a plurality of gate electrodes sequentially stacked on a surface of the substrate and extending from the cell array region to the connection region, a first source conductive pattern between the electrode structure and the substrate on the cell array region, and a cell vertical semiconductor pattern and a first dummy vertical semiconductor pattern that penetrate the electrode structure and the first source conductive pattern and extend into the substrate. The cell vertical semiconductor pattern may contact the first source conductive pattern. The first dummy vertical semiconductor pattern may be electrically insulated from the first source conductive pattern.

Disclosed is a nonvolatile memory device which includes a memory cell connected to a bit line and a word line; a page buffer electrically connected to the bit line and sensing data stored in the memory cell; and a control logic controlling the page buffer to vary a develop time of the bit line or a sensing node connected to the bit line according to a current temperature during a read operation.

Non-volatile memory device and read method thereof

A method of adjusting a threshold voltage of a ground selection transistor in a nonvolatile memory device includes providing a first voltage to a gate of a first ground selection transistor in a read operation and providing a second voltage to a gate of a second ground selection transistor in the read operation. The nonvolatile memory device includes at least one string, the string having string selection transistors, memory cells and the first and second ground selection transistors connected in series and stacked on a substrate.

Nonvolatile memory device and a method of adjusting a threshold voltage of a ground selection transistor thereof

Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

Three-dimensional semiconductor memory devices using direct strapping line connections

Provided is a flash memory device that can include a memory cell configured to store data, a local bit line that is connected to the memory cell, a global bit line that is connected to the local bit line, a discharge transistor that is connected to the global bit line, and that is configured to selectively connect the global bit line to a reference level responsive to a discharge control signal, and a discharge control circuit, that is connected to the discharge transistor via the discharge control signal, and that is configured to selectively disable the discharge transistor during an erase interval occurring before a verify interval of an erase verification operation carried out by the flash memory device.

Growing community of inventors

Suwon-si, South Korea

Bongyong Lee