Samsung Electronics Co., Ltd.

Bongtae Park

Jaejoo Shim

Jihye Kim

Jiyoung Kim

Jeehoon Han

Hyeong Geun Park

Jae-Joo Shim

Jaehoon Lee

Sungmin Hwang

Jang-Hyun You

Jae-Hwang Sim

Sungil Cho

Woo-jung Kim

Joo-Heon Kang

Jongyoon Choi

Hojun Seong

Choasub Kim

Dongsung Woo

Jaihyuk Song

Jaeyoun Kim

Manki Lee

Taegon Lee

Taewon Kang

Taechul Jung

A semiconductor device may include a first cell block including a first electrode structure including first electrodes stacked on a substrate, and first channels penetrating the first electrode structure, and a second cell block including a second electrode structure including second electrodes stacked on the substrate, and second channels penetrating the second electrode structure. The first and second electrode structures may extend in a first direction. The first electrode structure may have a first width in a second direction, and the second electrode structure may have a second width greater than the first width. A side surface of the first electrode structure and the first channel adjacent thereto may be apart from each other by a first distance, and a side surface of the second electrode structure and the second channel adjacent thereto may be apart from each other by a second distance different from the first distance.

Semiconductor device and electronic system including the same

Semiconductor device includes a substrate, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, separation regions penetrating the gate electrodes, extending in a second direction perpendicular to the first direction, and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, channel structures arranged in columns in the third direction and rows in the second direction and penetrating the gate electrodes between the separation regions, and bit lines extending in the third direction on the channel structures. The channel structures include a first group of channel structures repeatedly arranged and including three columns arranged with a first pitch and a second pitch smaller than the first pitch in order, and the bit lines are arranged with at least one pitch smaller than the second pitch in the second direction.

Integrated circuit memory devices having multi-pitch channel columns therein

A semiconductor device and a data storage system including the same, the semiconductor device including a substrate structure; a stack structure; a vertical memory structure; a vertical dummy structure; and an upper separation pattern, wherein hen viewed on a plane at a first height level, higher than a height level of a lowermost end of the upper separation pattern, the dummy channel layer includes a first dummy channel region facing the dummy data storage layer and a second dummy channel region facing the dummy data storage layer, the first dummy channel region having a thickness different from a thickness of the second dummy channel region.

Semiconductor device and data storage system including the same

A semiconductor device includes a substrate having a conductive region and an insulating region; gate electrodes including sub-gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate and extending in a second direction perpendicular to the first direction and gate connectors connecting the sub-gate electrodes disposed on the same level; channel structures penetrating through the gate electrodes and extending in the conductive region of the substrate; and a first dummy channel structure penetrating through the gate electrodes and extending in the insulating region of the substrate and disposed adjacent to at least one side of the gate connectors in a third direction perpendicular to the first and second directions.

Semiconductor device

A 3D semiconductor memory device includes an electrode structure on a substrate, the electrode structure including gate electrodes stacked in a first direction perpendicular to a top surface of the substrate, a vertical semiconductor pattern penetrating the electrode structure and connected to the substrate, and a data storage pattern between the electrode structure and the vertical semiconductor pattern. The data storage pattern includes first, second and third insulating patterns sequentially stacked. Each of the first to third insulating patterns includes a horizontal portion extending in a second direction parallel to the top surface of the substrate. The horizontal portions of the first, second and third insulating patterns are sequentially stacked in the first direction. At least one of the horizontal portions of the first and third insulating patterns protrudes beyond a sidewall of the horizontal portion of the second insulating pattern in the second direction.

Three-dimensional semiconductor memory devices

A semiconductor device may include a first conductive pattern having a line portion and a pad portion connected to the line portion on a substrate, a gate insulating pattern and a second conductive pattern sequentially stacked on the substrate, and a capping layer disposed on the first and second conductive patterns. A first trench is defined in an upper portion of the substrate adjacent to one side of the second conductive pattern, and the capping layer at least partially fills the first trench.

Semiconductor devices and methods of fabricating the same

A semiconductor device includes a plurality of lines disposed on a semiconductor substrate, and remaining line patterns disposed spaced apart from the lines on extensions from the lines. The lines include first end-portions adjacent to the remaining line patterns. The remaining line patterns include second end-portions adjacent to the lines. The first end-portions and second end-portions are formed to have mirror symmetry with respect to each other.

Semiconductor devices including separate line patterns

Method of fabricating semiconductor device and device fabricated thereby

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes lateral and upper hydrogen blocking patterns disposed to prevent hydrogen from diffusing into the cell array region. Accordingly, hydrogen is effectively prevented from being trapped in a tunnel dielectric, thereby improving the reliability of the semiconductor device. In the method, when a cell array contact plug is formed, a lateral hydrogen blocking pattern and an upper hydrogen blocking pattern are formed at the same time. Thus, an additional process for forming a hydrogen blocking pattern is unnecessary, thereby simplifying a process.

Semiconductor device and method of fabricating the same

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Seoul, South Korea

Bongtae Park