Samsung Electronics Co., Ltd.

Bongsoo Kim

Youngjun Kim

Seokhyun Kim

Sungwoo Kim

Hyeran Lee

Jinhyung Park

Hoju Song

Yoosang Hwang

Kiseok Lee

Keunnam Kim

Sunghee Han

Dongoh Kim

Hyeonok Jung

Hyosub Kim

Euna Kim

Chansic Yoon

Doohwan Lee

Joonsung Kim

Taeho Ko

Seokbong Park

Junghwan Park

Hyeongsun Hong

Gyeongmin Jin

Sungkwan Choi

Hakjoon Kim

Kyuhyun Lee

Jaebum Lee

A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.

Semiconductor memory device and method of manufacturing the same

An electronic device according to an embodiment may include: a Printed Circuit Board (PCB) including a first face and a second face; a semiconductor chip mounted on the second face; a conductive pad disposed on the second face; a solder resist layer disposed on the second face and including an aperture; an arc-shaped opening having an inner diameter and an outer diameter, disposed along an outer periphery of the conductive pad and in the aperture; and at least one external terminal disposed on the semiconductor chip and bonded to the conductive pad. The conductive pad may include: a first region having a smaller diameter than the outer diameter; and at least one second region extending from the first region in a first outer circumferential direction, and located at least in part between both ends of the opening. In addition, various embodiments recognized through the specification may also be possible.

Printed circuit board including conductive pad and electric device using the same

A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

Semiconductor memory devices

A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

Semiconductor and manufacturing method of the same

A semiconductor package includes; a lower connection structure, a semiconductor chip on the lower connection structure, an intermediate connection structure on the lower connection structure, a sealing layer covering the semiconductor chip, and an upper connection structure including a first upper insulating layer on the sealing layer, a first upper conductive pattern layer on the first upper insulating layer, and a first upper via penetrating the first upper insulating layer to directly connect the first upper conductive pattern layer to the intermediate connection structure. A height from an upper surface of the lower connection structure to an upper surface of the sealing layer is less than or equal to a maximum height from the upper surface of the lower connection structure to an upper surface of the intermediate connection structure.

Thin semiconductor package

A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

Semiconductor packages

Semiconductor devices

Semiconductor device and manufacturing method of the same

Semiconductor devices are provided. Each of the semiconductor devices may include a substrate including an active region that includes first and second regions. Each of the semiconductor devices may include a device isolation layer between the first and second regions of the active region. Each of the semiconductor devices may include a contact hole defined by recessed portions of the device isolation layer and the first region of the active region, respectively. Moreover, a topmost surface of the first region of the active region may define a bottommost portion of the contact hole. Related methods of forming semiconductor devices are also provided.

Semiconductor devices including a recessed active region, and methods of forming semiconductor devices including a recessed active region

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Yongin-si, South Korea

Bongsoo Kim