Ramschip, Inc.

Bongjoon Lee

Deoksoo Kim

Jaegan Ko

A signal receiving circuit includes first to third pulse generators; and a clock signal recovery unitfor generating a recovery clock signal RCLK and a recovery clock delay signal RCLKD, which is a signal obtained by delaying the recovery clock signal as much as a first delay time, using at least one of pulses including a first pulse, a second pulse, a third pulse, and first to third inversion pulses, wherein the clock signal recovery unit includes: a loop interruption circuit including an input node and an output node and turned on and off by at least one of the pulses; and a delay circuit having an input terminal connected to the output node and an output terminal connected to the input node. A signal value of the input node and a signal value of the output node are in an inverse relationship.

Growing community of inventors

Seongnam-si, South Korea

Bongjoon Lee