Samsung Electronics Co., Ltd.

Sungkyunkwan University

Bongjin Kuh

Hanmei Choi

Sukjin Chung

Beom Seok Kim

Sahwan Hong

Juyeon Kim

Joonghan Shin

Hakyu Seong

Changyong Kim

Jongsung Lim

Ki-chul Kim

Seunghwan Lee

Sunjung Kim

Kichul Kim

Taegon Kim

Jinhong Park

Sunguk Jang

Dohee Kim

Kook Tae Kim

Chunhyung Chung

Kongsoo Lee

Yongho Ha

Soojin Hong

Youngsun Kim

Musarrat Hasan

In-Sun Yi

Woocheol Jeong

Gabjin Nam

Soonwook Jung

Pyung Moon

Maksim Andreev

Junyeong Lee

Sunghwi Cho

Hoonsang Choi

Sangwook Lim

Jiwan Koo

Juhee Lee

Seunghwan Seo

Geonju Park

Woosung Ha

JeongMeung Kim

A semiconductor device includes a channel on a substrate. The channel includes a 2-dimensional material. A gate insulating layer is on a first portion of the channel. A gate electrode is on a portion of the gate insulating layer. First and second contact patterns are on second portions of the channel, respectively. Each of the first and second contact patterns includes a 2-dimensional material having an intercalation material disposed therein. First and second source/drain electrodes are on the first and second contact patterns, respectively. Each of the first and second source/drain electrodes includes a metal.

Semiconductor devices

A ferroelectric memory device according to the inventive concept includes a substrate having source/drain regions, an interface layer on the substrate, a high dielectric layer on the interface layer, a ferroelectric layer on the high dielectric layer, and a gate electrode layer on the ferroelectric layer. The high dielectric layer and the ferroelectric layer have phases of different crystal structures.

Ferroelectric memory device

An integrated circuit device includes: an active region extending in a first horizontal direction on a substrate; a first transistor at a first vertical level on the active region, the first transistor including a first source/drain region having a first conductive type; and a second transistor at a second vertical level that is higher than the first vertical level on the active region, the second transistor including a second source/drain region having a second conductive type and overlapping the first source/drain region in a vertical direction, wherein the first source/drain region and the second source/drain region have different sizes.

Integrated circuit devices including vertically stacked field effect transistors

A semiconductor device includes a plurality of patterns defined between a plurality of trenches and disposed on a substrate. A leaning control layer is disposed on sidewalls and bottoms of the plurality of trenches. A gap-fill insulating layer is disposed on the leaning control layer. At least one of the plurality of trenches has a different depth from one of the plurality of trenches adjacent thereto.

Semiconductor device including trench isolation layer and method of forming the same

Disclosed are a substrate processing apparatus and a method of cleaning the apparatus. The apparatus includes a process chamber, a support unit in the process chamber and configured to support a substrate, and a gas injection unit in the process chamber. The gas injection unit includes a first injection portion configured to inject a source gas, a second injection portion facing the first injection portion and configured to inject a reaction gas that reacts with the source gas, and a third injection portion configured to inject a cleaning gas that removes a reactant produced from the source gas and the reaction gas.

Substrate processing apparatus and method of cleaning the same

Disclosed are method and apparatus for forming a thin layer. The method for forming the thin layer comprises providing a substrate including patterns, forming a bonding layer on the substrate covering an inner surface of a gap between the patterns, forming a preliminary layer on the bonding layer filling the gap; and thermally treating the preliminary layer to form the thin layer. The bonding layer is a self-assembled monomer layer formed using an organosilane monomer. The preliminary layer is formed from a flowable composition comprising polysilane.

Method and apparatus for forming a thin layer

A deposition system which is configured to enable improved temperature uniformity of a heated substrate may include a susceptor provided in a chamber to hold a substrate, a reflection housing provided outside the chamber, a heating module including light sources provided in the reflection housing, and a reflection control module provided in the reflection housing between the heat sources and the chamber. The reflection control module may be configured to reflect light, which propagates along a first trajectory from the light sources toward a center region of the substrate, to propagate along a second trajectory toward an edge region of the substrate, thereby providing improved substrate irradiance uniformity and thus improved substrate temperature uniformity. Improved substrate temperature uniformity may result in improved thickness uniformity of layers provided on the substrate in a deposition process.

Deposition system for forming thin layer

A semiconductor device includes a substrate, a first insulation layer formed on the substrate in a first region, a photon absorption seed layer formed on the first insulation layer in the first region and on the substrate in a second region separate from the first region, and a photon absorption layer formed on the photon absorption seed layer in the first region. The photon absorption seed layer has a particular structure that may assist in reducing dislocation density in a region that includes a photon absorption layer.

Semiconductor device and method for fabricating the same

A semiconductor device includes a first semiconductor layer including a recess region and protrusions defined by the recessed region, first insulating patterns provided on the protrusions and extending to sidewalls of the protrusions, and a second semiconductor layer to fill the recess region and cover the first insulating patterns. The protrusions includes a first group of protrusions spaced apart from each other in a first direction to constitute a row and a second group of protrusions spaced from the first group of protrusions in a second direction intersecting the first direction and spaced from each other in the first direction to constitute a row. The second group of protrusions are shifted from the first group of protrusions in the first direction.

Semiconductor device with an epitaxial layer and method of fabricating the same

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a plurality of unit cells provided on a semiconductor substrate. Each of the unit cells may include a buried insulating pattern buried in the semiconductor substrate, a first active pattern provided on the buried insulating pattern, and a second active pattern provided on the buried insulating pattern and spaced apart from the first active pattern. The buried insulating pattern may define a unit cell region, in which each of the unit cells may be disposed.

Semiconductor device and method of fabricating the same

In one embodiment, the method of forming a dielectric layer includes supplying a first precursor at a temperature less than 400 degrees Celsius to a chamber including a substrate. The first precursor includes dysprosium. A first reaction gas is supplied to the chamber to react with the first precursor. A second precursor is supplied at a temperature less than 400 degrees Celsius to the chamber, and the second precursor includes scandium. A second reaction gas is supplied to the chamber to react with the second precursor.

Method of forming dielectric including dysprosium and scandium by atomic layer deposition and integrated circuit device including the dielectric layer

Growing community of inventors

Suwon-si, South Korea

Bongjin Kuh