Intel Corporation

Hewlett-packard Development Company, L.P.

Bongjin Jung

James R Vash

Pritpal S Ahuja

Yen-Cheng Liu

Jeffrey D Chamberlain

Arvind Srinivasan

Robert G Southworth

David Arditti Ilitzky

Vida Vakilotojar

Rishan Tan

John Greth

Ren Wang

Vedaraman Geetha

Bahaa Fahim

Zeshan A Chishti

Sailesh Kottapalli

Eric R Delano

Aamer Jaleel

Adrian C Moga

Nazar Syed Haider

Henk G Neefs

Ganesh Kumar

Tejpal Singh

Judson S Leonard

Gaspar Mora Porta

Karl S Papadantonakis

Donald C Soltis, Jr

Chung-Chi Wang

Matthew C Mattina

Terry C Huang

Carl Geisler Ramey

Neil J Achtman

Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer. In some examples, a fetch scheduler is used to adapt an amount of interface overspeed to reduce packet fetching latency while attempting to prevent fabric saturation based on a switch fabric load level, wherein the fetch scheduler is to control the jitter threshold level for the buffer by forcing a jitter threshold level based on switch fabric load level and latency profile of the switch fabric.

Dynamic virtual cut-through and dynamic fabric bandwidth allocation between virtual cut-through and store-and-forward traffic

Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.

Maintaining bandwidth utilization in the presence of packet drops

Methods and apparatus relating to improving the value of F-state by increasing a local caching agent's data forwarding are described. In one embodiment, the opportunity for forwarding from a local caching agent is improved by allowing the local caching agent to keep an F-state copy of the line while sending an S-state copy to the requestor (e.g., in response to a non-ownership read operation). Other embodiments are also disclosed.

Value of forward state by increasing local caching agent forwarding

A shared mesh comprises a mesh station. The mesh station is used to couple to at least a first core component and a second core component. The mesh station includes a logic unit. The mesh station is shared by at least the first core component and the second core component. A memory is coupled to the mesh station.

Shared mesh

In accordance with embodiments disclosed herein, there is provided systems and methods for providing a virtual shared cache mechanism. A processing device includes a plurality of clusters allocated into a virtual private shared cache. Each of the clusters includes a plurality of cores and a plurality of cache slices co-located within the plurality of cores. The processing device also includes a virtual shared cache including the plurality of clusters such that the cache data in the plurality of cache slices is shared among the plurality of clusters.

Virtual shared cache mechanism in a processing device

Methods and apparatus relating to an inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline are described. In one embodiment, logic may arbitrate between two queues based on various rules. The queues may store data including local or remote requests, data responses, non-data responses, external interrupts, etc. Other embodiments are also disclosed.

Inter-queue anti-starvation mechanism with dynamic deadlock avoidance in a retry based pipeline

Methods, apparatus and systems for facilitating one-way ordering of otherwise independent message classes. A one-way message ordering mechanism facilitates one-way ordering of messages of different message classes sent between interconnects employing independent pathways for the message classes. In one aspect, messages of a second message class may not pass messages of a first message class. Moreover, when messages of the first and second classes are received in sequence, the ordering mechanism ensures that messages of the first class are forwarded to, and received at, a next hop prior to forwarding messages of the second class.

Apparatus, system, and methods for facilitating one-way ordering of messages

Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed.

Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline

Systems, apparatus, and method of monitoring synchronization in a distributed cache are described. In an exemplary embodiment, a first and second processing core process a first and second thread respectively. A first and second distributed cache slices store data for either or both of the first and second processing cores. A first and second core interface co-located with the first and second processing cores respectively maintain a finite state machine (FSM) to be executed in response to receiving a request from a thread of its co-located processing core to monitor a cache line in the distributed cache.

Monitoring thread synchronization in a distributed cache

Methods and apparatus relating to system-wide quiescence and per-thread transaction fence in a distributed caching agent are described. Some embodiments utilize messages, counters, and/or state machines that support system-wide quiescence and per-thread transaction fence flows. Other embodiments are also disclosed.

System-wide quiescence and per-thread transaction fence in a distributed caching agent

Each processor in a distributed shared memory system has an associated memory and a coherence directory. The processor that controls a memory is the Home processor. Under certain conditions, another processor may obtain exclusive control of a data block by issuing a Load Lock instruction, and obtaining a writeable copy of the data block that is stored in the cache of the Owner processor. If the Owner processor does not complete operations on the writeable copy of the data prior to the time that the data block is displaced from the cache, it issues a Victim To Shared message, thereby indicating to the Home processor that it should remain a sharer of the data block. In the event that another processor seeks exclusive rights to the same data block, the Home processor issues an Invalidate message to the Owner processor. When the Owner processor is ready to resume operation on the data block, the Owner processor again obtains exclusive control of the data block by issuing a Read-with Modify Intent Store Conditional instruction to the Home processor. If the Owner processor is still a sharer, a writeable copy of the data block is sent to the Owner processor, who completes modification of the data block and returns it to the Home processor with a Store Conditional instruction.

Mechanism for handling load lock/store conditional primitives in directory-based distributed shared memory multiprocessors

Growing community of inventors

Westford, MA, United States of America

Bongjin Jung