Adeia Semiconductor Bonding Technologies Inc.

Bong-Sub Lee

Charles Gerard Woychik

Arkalgud R Sitaram

Cyprian Emeka Uzoh

Liang Wang

Laura Wills Mirkarimi

Andrew Cao

Interposer circuitry () is formed on a possibly sacrificial substrate () from a porous core (') covered by a conductive coating (&#x2033;) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

Interposers with electrically conductive features having different porosities

A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.

Structure and method for integrated circuits packaging with increased density

Interposers

Method for fabrication of interconnection circuitry with electrically conductive features passing through a support and comprising core portions formed using nanoparticle-containing inks

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Mountain View, CA, United States of America

Bong-Sub Lee