Samsung Electronics Co., Ltd.

Hyundai Motor Company

Kia Motors Corporation

Samsung Electro-Mechanics Co., Ltd.

Samsung Display Co., Ltd.

Hyundai Dymos Inc.

Techwing Co., Ltd.

Dymos Incorporated

Duckil Industry Co., Ltd.

Bong Soo Kim

Ji Young Kim

Sang Do Park

Je Min Park

Jong Kweon Pyun

Hak Gyun Kim

Se Myeong Jang

Ki Hwan Kim

Tae Gon Kim

Sung Hwan Kim

Gil Ju Kim

Dong Woo Jeong

Sung-Min Park

Seung Hyun Song

Su Jin Jung

Jun Yeol Heo

Sung Uk Jang

Young Dae Cho

Yuichiro Sasaki

Kyung In Choi

Abraham Yoo

Alexander Schmidt

Yoshiya Moriyama

Heung Soon Lee

Sung Min Park

Dong Jin Lee

Dae Hee Lee

In Ho Lee

Tae Hoon Lee

Chan Ho Jeong

Do Young Jeong

Yun Sung Na

Jong Hyun Choung

In Gu Jeon

Myung Ho Lee

Jae Gyun Shim

Dong Hyun Yo

Joon Seok Oh

Moon Young Jeong

Tae Ho Ko

Sang Nam Park

Myeong Ho Hong

Hyeon Kyun Noh

Seung Su Han

Jong Yun Lee

Yeong Uk Kim

Sang-Nam Park

Dong Yeoul Kim

Yong-Hee Shin

Choung Min Joung

A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

Semiconductor devices

A method of forming a semiconductor device includes forming first sacrificial patterns on a lower structure, forming first remaining mask layers having a 'U' shape between the first sacrificial patterns to be in contact with the first sacrificial patterns, forming first remaining mask patterns by pattering the first remaining mask layers, each of the first remaining mask patterns including a horizontal portion, parallel to an upper surface of the lower structure, and a vertical portion, perpendicular to the upper surface of the lower structure, forming second mask patterns spaced apart from the vertical portions of the first remaining mask patterns, removing the first sacrificial patterns remaining after forming the second mask patterns, and forming first mask patterns by etching the horizontal portions of the first remaining mask patterns.

Method of forming semiconductor device

A semiconductor device includes a plurality of lower electrode structures disposed on a substrate, and a supporter pattern disposed between pairs of lower electrode structures of the plurality of lower electrode structures. The semiconductor device further includes a capacitor dielectric layer disposed on surfaces of each of the plurality of lower electrode structures and the supporter pattern, and an upper electrode disposed on the capacitor dielectric layer. The plurality of lower electrode structures includes a first lower electrode and a second lower electrode disposed on the first lower electrode and having a cylindrical shape. The first lower electrode has a pillar shape. The first lower electrode includes an insulating core. The insulating core is disposed in the first lower electrode. An outer side surface of the first lower electrode and an outer side surface of the second lower electrode are coplanar.

Semiconductor device having hybrid capacitors

A method includes forming hard mask patterns by depositing a support mask layer, a polycrystalline silicon layer, and a hard mask layer on a substrate and etching the hard mask layer, forming pre-polycrystalline silicon patterns by etching the polycrystalline silicon layer using the hard mask patterns as an etch mask, oxidizing side surfaces of the pre-polycrystalline silicon patterns to form polycrystalline silicon patterns and a silicon oxide layer, forming spacer patterns covering sides of the silicon oxide layer, forming a sacrificial layer on a top surface of the support mask layer to cover the silicon oxide layer and the spacer patterns, etching the sacrificial layer and the silicon oxide layer, forming support mask patterns by etching the support mask layer using the polycrystalline silicon patterns and the spacer patterns as an etch mask, and forming activation pins by etching the substrate using the support mask patterns as an etch mask.

Method of manufacturing semiconductor device

A semiconductor device is provided. The semiconductor device includes a first substrate, an active region defined by an isolation film in the first substrate, an oxide semiconductor layer on the first substrate in the active region, and not comprising silicon, a recess inside the oxide semiconductor layer, and a gate structure filling the recess, comprising a gate electrode and a capping film on the gate electrode, and having an upper surface on a same plane as an upper surface of the active region.

Semiconductor device

A fan-out semiconductor package includes: a frame including first to third insulating layers, a first wiring layer disposed on a first surface of the first insulating layer and embedded in the second insulating layer, and a second wiring layer disposed on the third insulating layer, and having a through-hole penetrating through the first to third insulating layers; a semiconductor chip disposed in the through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface; an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole; and a connection structure disposed on the frame and the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads. The first and second wiring layers are electrically connected to the connection pads.

Fan-out semiconductor package

A fan-out semiconductor package includes: a core member having a through-hole; a semiconductor chip disposed in the through-hole of the core member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant covering at least portions of the core member and the semiconductor chip and filling at least portions of the through-hole; and a connection member disposed on the core member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The core member has a recess portion penetrating through at least portions of the core member, and at least a portion of the recess portion is filled with the encapsulant.

A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

Method of forming a semiconductor device having impurity region

A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, a first encapsulant encapsulating at least portions of the first connection member and the semiconductor chip, a second connection member disposed on the first connection member and the semiconductor chip. The first connection member and the second connection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip. The fan-out semiconductor package may have excellent rigidity, may be thinned, and may be manufactured in a simplified process.

Semiconductor device having impurity region

An array substrate for display devices is provided. According to an exemplary embodiment, the array substrate for display device includes: a plurality of gate lines that extend along a first direction; and a data line that is formed by connecting a plurality of first sub-data lines extending along a second direction and a plurality of second sub-data lines extending along a third direction, wherein the gate lines overlap the second sub-data lines with an insulating layer interposed therebetween.

Array substrate for display devices

An electronic component embedded substrate and a method of manufacturing an electronic component embedded substrate, The substrate includes a first via passing through a part of an insulating portion of the substrate to an electrode of the electronic component, and a second via passing through a part of the insulating portion to the conductor pattern. The second via has a contact portion with a smaller cross-sectional area than the cross-sectional area of a contact portion of the first via.

Electronic component embedded substrate and method of manufacturing electronic component embedded substrate

Growing community of inventors

Suwon-si, South Korea

Bong Soo Kim