Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Bong-Jun Lee

Sung-Man Kim

Hong-Woo Lee

Beom-jun Kim

Shin-Tack Kang

Byeong-Jae Ahn

Jong-Oh Kim

Myung-Koo Hur

Jung Hwan Hwang

Beom Jun Kim

Hyeong-Jun Park

Yeon-Kyu Moon

You Mee Hyun

Seong Yeol Syn

Jong-Hwan Lee

Yu-Jin Kim

Kyung-Wook Kim

Seul Ki Kim

Dong Wuuk Seo

Sung Man Kim

Duk-Sung Kim

Dong-Wuuk Seo

Gyu-Tae Kim

Min Hee Son

Byeong-jae Ahn

Jin Yun Kim

Jong-Hyuk Lee

Yong-Woo Lee

Hyuk-Jin Kim

Jin-Suk Seo

Sun-Kyu Joo

Myung-Sub Lee

Ju-Hyeon Baek

Jae-min Shin

Sun-Hyung Kim

Seung-Hwan Moon

Jae-Ho Lee

Seong-Young Lee

Nam-Soo Kang

Beomjun Kim

Yong-Soon Lee

Hyun-Ho Kang

Ji-Young Jeong

Sang-Jin Jeon

Jong Woong Chang

Yeo-Geon Yoon

Haeng-Won Park

Sungman Kim

Hyeon-Hwan Kim

Ju Hee Lee

Ji Young Jeong

Hong-Kyu Kim

Yun Chan Heo

Sun-Kwun Son

Seung Han Jo

Ju Hyeon Baek

Byung-Su Oh

Jae-seung Kim

Young-Geol Song

Jae Yoon Jung

Chung-Hun Ha

Kyung-Seob Choi

A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

Display panel

A gate driving circuit including a plurality of stages connected with each other and configured to output a plurality of gate signals. An n-th (n is a natural number) stage including a gate output part including a first transistor connected between a clock signal and an output node outputting an n-th gate signal, the first transistor having a gate electrode connected to a control node, a carry part connected between the clock signal and a carry node outputting an n-th carry signal, a first node control part connected between the output node and a first low voltage, and a second node control part including at least one transistor connected between the control node and a second low voltage different from the first low voltage.

Gate driving circuit and display apparatus having the same

A display panel includes a first substrate, a second substrate which faces the first substrate, is smaller than the first substrate so that an edge of the first substrate is exposed in a plan view, a fixing member disposed on the exposed edge of the first substrate, and a bonding member disposed between the first substrate and the fixing member.

Display panel and display apparatus having the same

A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Liquid crystal display

A display, includes: a substrate; first signal lines (FSLs) at least partially recessed in the substrate and extending in substantially a direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

A display device includes a signal line disposed on a substrate. A signal input line is disposed on the substrate and connected to a driver. A first insulating layer is disposed on the signal line. A second insulating layer is disposed on the signal input line and the first insulating layer. First contact holes penetrate the first insulating layer and the second insulating layer and expose a portion of the signal line. Second contact holes penetrate the second insulating layer and expose a portion of the signal input line. A connecting member connects the signal line and the signal input line through the first and the second contact holes and is disposed on the second insulating layer. The first and the second contact holes are alternately arranged in the second insulating layer.

Display device

A display panel includes a plurality of pixels disposed in an active area and arranged substantially in a matrix form including a pixel row and a pixel column, a first gate line disposed adjacent to a first side n of the pixel row and connected to a first pixel in the pixel row, a second gate line disposed adjacent to a second side of the pixel row and connected to a second pixel in the pixel row, a plurality of data lines crossing the first and second gate lines, where the pixels in a pair of adjacent pixel columns are connected to a same data line, and a blocking pattern which overlaps a pixel column disposed in an end portion of the active area.

Display panel, method of manufacturing the display panel and display apparatus

A liquid crystal display includes: a first substrate; a gate line and a common voltage line that are on the first substrate; a gate insulating layer on the gate line and the common voltage line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode that are on the semiconductor layer; a pixel electrode on the data line and the drain electrode; a passivation layer on the pixel electrode; a common electrode on the passivation layer; a second substrate; and a liquid crystal layer interposed between the first and second substrates. The pixel electrode contacts the drain electrode via a first contact hole, the common electrode contacts the common voltage line via a second contact hole in the gate insulating layer and the passivation layer, and the first and second contact holes are adjacently disposed in a thin film transistor forming region.

Liquid crystal display having contact holes adjacently disposed in thin film transistor forming region

A display device includes a first insulation substrate, a gate line disposed on the first insulation substrate, a semiconductor layer disposed on the gate line, a data line insulated from and crossing the gate line and including a source electrode and a drain electrode facing the source electrode, a first insulating layer disposed on the source electrode and the drain electrode, a pixel electrode electrically connected to the drain electrode, a second insulating layer disposed on the pixel electrode, a common electrode disposed on the second insulating layer, and a shielding pattern part disposed on a same layer as the pixel electrode and overlapping the data line.

Display device and manufacturing method thereof

A gate driving circuit is provided which includes a plurality of stages cascade-connected with each other and outputting a plurality of gate signals. An n-th (n is a natural number) stage includes a gate output part, a first node control part and a carry part. The gate output part includes a first transistor. The first transistor outputs a high voltage of a clock signal to a high voltage of an n-th gate signal in response to a high voltage of a control node. The first node control part is connected to the control node to control a signal of the control node and includes at least one transistor having a channel longer than the channel length of the first transistor. The carry part outputs the high voltage of the clock signal to an n-th carry signal in response to the signal of the control node.

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Seoul, South Korea

Bong-Jun Lee