Samsung Electronics Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Bong Ju Cho

Jin Su Kim

Jeong Ho Lee

Young Gwan Ko

Myung Sam Kang

Shang Hoon Seo

Jeong Il Lee

Moon Il Kim

Young Chan Ko

Ki Ju Lee

Jeong Seok Kim

Jeong Ii Lee

A fan-out semiconductor package including a first redistribution layer; a first semiconductor chip on the first redistribution layer; an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip; a molded layer covering the interconnector and side surfaces of the first semiconductor chip; and a second redistribution layer on the molded layer, wherein the interconnector includes a metal ball and is electrically connected to the first redistribution layer, the second redistribution layer includes a first line wiring, and a first via electrically connected to the first line wiring, the first via is connected to the interconnector, and a part of the first via is in the molded layer.

Fan-out semiconductor package

A method includes forming a first package structure including a first connection member including a first redistribution layer, a first frame having a first through-portion, a first semiconductor chip having a connection pad electrically connected to the first redistribution layer, and a first encapsulant covering a portion of each of the first frame and the first semiconductor chip, forming a second package structure including a second connection member including a second redistribution layer, a second semiconductor chip having a second connection pad, and a second encapsulant covering a portion of the second semiconductor chip, forming a first through-via, the first through-via electrically connecting to the second redistribution layer, and laminating the first package structure on the second package structure. After the laminating, the first through-via penetrates through the first frame, the first encapsulant, and a portion of the first connection member, and is electrically connected to the first redistribution layer.

Semiconductor package

A semiconductor package includes a first connection member including a first redistribution layer, a first frame disposed on the first connection member, a first semiconductor chip disposed on a first through-portion and having a connection pad, a first encapsulant covering a portion of each of the first frame and the first semiconductor chip and filling at least a portion of the first through-portion, a second connection member disposed on the first encapsulant and including a second redistribution layer, a second semiconductor chip disposed on the second connection member and having a second connection pad, a second encapsulant covering a portion of the second semiconductor chip, and a first through-via penetrating through the first frame, the first encapsulant, and a portion of the first connection member, and electrically connecting the first and second redistribution layers to each other.

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; first metal bumps disposed on the connection pads; second metal bumps disposed on an uppermost wiring layer of the wiring layers; an encapsulant covering at least portions of each of the frame, the semiconductor chip, and the first and second metal bumps and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads and the uppermost wiring layer through the first and second metal bumps.

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers disposed on the insulating layers, and connection via layers penetrating through the insulating layers and electrically connecting the wiring layers to each other, and having a recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and an active surface of the semiconductor chip and including one or more redistribution layers electrically connecting the wiring layers and the connection pads to each other, in which the recess portion includes walls having different inclined angles.

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a guide pattern disposed adjacent to a wall of the recess portion and disposed in the frame. An edge of the bottom surface of the recess portion has a groove portion.

Growing community of inventors

Suwon-si, South Korea

Bong Ju Cho