Samsung Electronics Co., Ltd.

Kookje Electric Korea Co., Ltd.

Bong-jin Kuh

Yong-Ho Ha

Ji-Hye Yi

Han-Mei Choi

Jeong-Hee Park

Doo-Hwan Park

Han-Bong Ko

Ki-chul Kim

Jun-Soo Bae

Hee-Ju Shin

Sang-Wook Lim

Joong-han Shin

Gwan-Hyeob Koh

Se-Ho Lee

Su-Jin Ahn

Young-Nam Hwang

Sung-lae Cho

Kyung-Chang Ryoo

Chang-Wook Jeong

Byung-Hong Chung

Horii Hideki

Su-Youn Lee

Jong-sung Lim

Ju-Chul Park

Yong-Sung Park

Jang-Eun Lee

Yoon-jong Song

Yong-Suk Tak

Wan-don Kim

Soon-Oh Park

Eun-ha Lee

Sang-Don Nam

Choong-Man Lee

Hee-Seok Kim

Sung-ho Kang

Soon-Wook Jung

Yong-Kyu Joo

Sung-Ho Heo

Hyun-Jeong Yang

Wanit Manorotkul

Dmitry Mikulik

Ji-Eun Lee

Jung-Min Oh

Tae-Gon Kim

Young-sub You

Je-Woo Han

Gyung-Jin Min

Jong-Hoon Kang

Nam-goo Cha

Jun-ho Yoon

Sang-Ryol Yang

Jung-Yun Won

Sang-Yoon Woo

Sang-ryol Yang

Eun-Young Jo

Tae-Jin Park

Yong-Moon Jang

Supakit Charnvanichborikarn

Jae-hee Lee

Jeong-meung Kim

Soon-wook Jung

Young-Sub Yoo

A laser annealing apparatus includes a laser oscillating structure, an oscillator, a beam expanding telescope, a first power meter, and a second power meter. The laser oscillating structure emits a first laser beam of a first wavelength and first beam cross-section to a substrate in a chamber including an optical window. The oscillator emits a second laser beam, of a second wavelength different from the first wavelength, to the substrate. The beam expanding telescope is on an optical path for the second laser beam and expands the second laser beam to a second beam cross-section. The first and second power meters measure energy of the second laser beam and a third laser beam, generated as the second laser beam is reflected by the substrate. The first beam cross-section and the second beam cross-section may be equal.

Laser annealing apparatus for semiconductors having multiple laser energy measuring means

There is provided a nanostructure semiconductor light emitting device including a base layer formed of a first conductivity-type semiconductor, a first insulating layer disposed on the base layer and having a plurality of first openings exposing partial regions of the base layer, a plurality of nanocores disposed in the exposed regions of the base layer and formed of the first conductivity-type semiconductor, an active layer disposed on surfaces of the plurality of nanocores positioned to be higher than the first insulating layer, a second insulating layer disposed on the first insulating layer and having a plurality of second openings surrounding the plurality of nanocores and the active layer disposed on the surfaces of the plurality of nanocores, and a second conductivity-type semiconductor layer disposed on the surface of the active layer positioned to be higher than the second insulating layer.

Nano-structured semiconductor light-emitting element

In a method of forming an epitaxial layer, an etching gas may be decomposed to form decomposed etching gases. A source gas may be decomposed to form decomposed source gases. The decomposed source gases may be applied to a substrate to form the epitaxial layer on the substrate. A portion of the epitaxial layer on a specific region of the substrate may be etched using the decomposed etching gases. Before the etching gas is introduced into the reaction chamber, the etching gas may be previously decomposed. The decomposed etching gases may then be introduced into the reaction chamber to etch the epitaxial layer on the substrate. As a result, the epitaxial layer on the substrate may have a uniform distribution.

Method of forming an epitaxial layer on a substrate, and apparatus and system for performing the same

An IC device includes a polycrystalline silicon thin film interposed between a first level semiconductor circuit and a second level semiconductor circuit which are formed on a substrate and disposed to vertically overlap each other. The polycrystalline silicon thin film includes at least one silicon single crystal. The at least one silicon single crystal includes a flat horizontal portion, which provides an active region of the second level semiconductor device, and a pin-shaped protruding portion protruding from the flat horizontal portion toward the first level semiconductor device.

Integrated circuit device including polycrystalline semiconductor film and method of manufacturing the same

A semiconductor device includes a plurality of lower electrodes having a vertical length greater than a horizontal width on a substrate, a supporter disposed between the lower electrodes, an upper electrode disposed on the lower electrodes, and a capacitor dielectric layer disposed between the lower electrodes and the upper electrode. The supporter includes a first element, a second element, and oxygen, an oxide of the second element has a higher band gap energy than an oxide of the first element, and the content of the second element in the supporter is from about 10 at % to 90 at %.

Semiconductor device having supporter

Semiconductor device having supporter and method of forming the same

A semiconductor device includes a single crystalline substrate, an electrical element and an optical element. The electrical element is disposed on the single crystalline substrate. The electrical element includes a gate electrode extending in a crystal orientation &#x3c;110&#x3e; and source and drain regions adjacent to the gate electrode. The source region and the drain region are arranged in a direction substantially perpendicular to a direction in which the gate electrode extends. The optical element is disposed on the single crystalline substrate. The optical element includes an optical waveguide extending in a crystal orientation &#x3c;010&#x3e;.

Semiconductor devices

A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer.

Methods of forming epitaxial layers

A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.

Integrated circuit devices including electrode support structures and methods of fabricating the same

Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.

Method of fabricating semiconductor device

Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.

Methods of forming phase-changeable memory devices including an adiabatic layer

A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a &#x3c;100&#x3e; crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets.

Method of forming a thin layer structure

A method of manufacturing a phase-change memory device comprises forming a contact region on a substrate, forming a lower electrode electrically connected to the contact region, forming a phase-change material layer on the lower electrode using a chalcogenide compound target including carbon and metal, or carbon, nitrogen and metal, and forming an upper electrode on the phase-change material layer.

Methods for manufacturing a phase-change memory device

Growing community of inventors

Gyeonggi-do, South Korea

Bong-jin Kuh