Samsung Electronics Co., Ltd.

University of California

Bong Il Park

Jae Gon Lee

Jae Young Lee

Andrew B Kahng

Kwang Ho Kim

Jong Ho Roh

Taek Kyun Shin

Jin Ook Song

Dong Keun Kim

Seok Hyeong Kang

Jang Ho Cho

Yung Hei Lee

Moo Kyung Kang

A clock generation circuit having a deskew function and a semiconductor integrated circuit device including the same are provided. The clock generation circuit includes a clock gating circuit configured to gate an input clock signal based on a first waveform signal to generate a first output signal, a flip-flop configured to receive the input clock signal and a second waveform signal and to generate a second output signal, and an OR circuit configured to perform an OR operation on the first output signal and the second output signal to generate an output clock signal having a period which is N times a period of the input clock signal.

Clock generation circuit having deskew function and semiconductor integrated circuit device including same

A display system is provided. The display system includes a perframe controller configured to receive a frame synchronization signal and to change values of M and N in synchronization with at least one pulse of the frame synchronization signal, where M and N are natural numbers; and a fractional divider configured to generate and output a pixel clock signal by dividing an input clock signal by a division ratio of N/M.

Display system

A hierarchical power management circuit includes N power management circuits respectively included in N power domains each including at least one intellectual property (IP), wherein N is a natural number greater than one. The i-th (1&#x3c;i&#x3c;N) power management circuit from among the N power management circuits manages supply of power to an (i+1)th power domain from among the N power domains in response to a power management request signal output from a first power management circuit from among the N power management circuits.

Hierarchical power management circuit, power management method using the same, and system on chip including the hierarchical power management circuit

A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage.

Data-retained power-gating circuit and devices including the same

Disclosed is an integrated circuit device including a plurality of power domain blocks, which includes a core power domain block. A power control circuit is configured to control power supplied to each of the plurality of power domain blocks independently responsive to control communication from the core power domain block. The power control circuit includes a plurality of power clusters corresponding to the plurality of power domain blocks, respectively. The plurality of power clusters control power supplied to the plurality of power domain blocks, respectively, independently responsive to the control communication from the core power domain block.

System on chip, devices having the same, and method for power control of the SOC

Growing community of inventors

Seongnam-si, South Korea

Bong Il Park