Samsung Electronics Co., Ltd.

Bong-hyun Kim

Han-jin Lim

Seok-Woo Nam

Joon Hyuk Kim

Taek-Soo Jeon

Dong-Kak Lee

Won-Seok Yoo

Jae-hong Seo

Dae-Hyun Kim

Hyeon-Deok Lee

Soo-jin Hong

Yong-Woo Hyung

Dong-Woon Shin

Ho-kyun An

Young-sun Kim

Jung-Hwan Kim

Sung-Tae Kim

Young-Jin Kim

Ki-chul Kim

Jung-Hyun Lee

Dong-Chan Kim

Jae-hyoung Choi

Chang-min Park

Jae-Soon Lim

Hong-bae Park

Young-Geun Park

Young-sub You

Gab-Jin Nam

Sang-Yeol Kang

Hyo-Jung Kim

Hyun-Jin Shin

Woo-Sung Lee

Kyoung-Seok Kim

Kyoung-Ryul Yoon

Man-Sug Kang

Seung-Mok Shin

Jai-Dong Lee

Jae-young Park

Eun-Kuk Chung

Yong-Sun Lee

Su-Min Kim

In-Sang Jeon

Wook-Yeol Yi

Myang-Sik Han

Jong-wan Kwon

Hun-Hyeoung Lim

Tae-Soo Park

Beom-jong Kim

Heon-Heoung Leam

Chang-Mu An

An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

Electrode structure, method of fabricating the same, and semiconductor device including the electrode structure

A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

Methods of fabricating memory devices using wet etching and dry etching

A precursor composition for forming a silicon dioxide film on a substrate, the precursor composition including at least one precursor compound represented by the following chemical formulas (1), (2), and (3):HSiA(NRR)&#x2003;&#x2003;(1)HSi(NAR)&#x2003;&#x2003;(2)HSi(R)(R)&#x2003;&#x2003;(3)wherein, independently in the chemical formulas (1), (2), and (3), H is hydrogen, x is 0 to 3, Si is silicon, A is a halogen, y is 1 to 4, N is nitrogen, and R, R, R, and Rare each independently selected from the group of H, aryl, perhaloaryl, Calkyl, and Cperhaloalkyl, and Ris aryl in which at least one hydrogen is replaced with a halogen or Calkyl in which at least one hydrogen is replaced with a halogen.

Precursor composition for deposition of silicon dioxide film and method for fabricating semiconductor device using the same

A semiconductor device includes a substrate having a conductive area, a first pattern formed on the substrate and having a contact hole through which the conductive area is exposed, and a contact plug in the contact hole. The contact plug includes first and second silicon layers. The first silicon layer, formed from a first compound including at least two silicon atoms, is formed in the contact hole to contact a top surface of the conductive area and a side wall of the first pattern. The second silicon layer, formed from a second compound including a number of silicon atoms less than the number of the silicon atoms of the first compound, is formed on the first silicon layer and fills a remaining space of the contact hole, the second silicon layer being spaced apart from the first pattern at an entrance of the contact hole.

Semiconductor device including contact plug and method of manufacturing the same

The inventive concept provides methods of manufacturing semiconductor devices having a fine pattern. In some embodiments, the methods comprise forming an etch-target film on a substrate, forming a first mask pattern on the etch-target film, forming a second mask pattern by performing an ion implantation process in the first mask pattern, and etching the etch-target film using the second mask pattern.

Methods of forming a fine pattern on a substrate and methods of forming a semiconductor device having a fine pattern

In a method of forming a capacitor, a seed stopper and a sacrificial layer is formed on an insulating interlayer having a plug therethrough. An opening is formed through the sacrificial layer and the seed stopper to expose the plug. A seed is formed on an innerwall of the opening. A lower electrode is formed covering the seed on the innerwall of the opening. The sacrificial layer and the seed are removed. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

Methods of forming a capacitor structure and methods of manufacturing a semiconductor device using the same

Provided are methods of fabricating capacitors of semiconductor devices, the methods including: forming a lower electrode on a semiconductor substrate, performing a pre-process operation on the lower electrode for suppressing deterioration of the lower electrode during a process, forming a dielectric layer on the lower electrode using a source gas and an ozone gas, and forming an upper electrode on the dielectric layer, wherein the pre-process operation and the forming of the dielectric layer may be performed in one device capable of atomic layer deposition.

Methods of fabricating stack type capacitors of semiconductor devices

Example embodiments of the present invention relate to methods of manufacturing a semiconductor device. Other example embodiments of the present invention relate to methods of manufacturing a semiconductor device having a gate electrode. In the method of manufacturing the semiconductor device, a gate electrode may be formed on a semiconductor substrate. Damage in the semiconductor substrate and a sidewall of the gate electrode may be cured, or repaired, by a radical re-oxidation process to form an oxide layer on the semiconductor substrate and the gate electrode. The radical re-oxidation process may be performed by providing a nitrogen gas onto the semiconductor substrate while increasing a temperature of the semiconductor substrate to a first temperature to passivate a surface of the gate electrode under a nitrogen gas atmosphere, providing an oxygen gas onto the semiconductor substrate while increasing the temperature from a first temperature to a second temperature to perform a first oxidation process and/or performing a second oxidation process at the second temperature.

Methods of manufacturing a semiconductor device

A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.

Method of forming high dielectric film using atomic layer deposition and method of manufacturing capacitor having the high dielectric film

A tunnel dielectric layer is formed on a semiconductor device. A floating gate layer is formed on the tunnel dielectric layer. An intergate dielectric layer (ONO layer) is formed on the floating gate layer. An in-situ doped silicon is deposited on the intergate dielectric layer to form a control gate layer and then, an annealing is carried out. The control gate layer, the intergate dielectric layer, and the floating gate layer are patterned through a photolithographic process. The phase transformation of the control gate silicon layer does not occur during a subsequent gate oxidation process to reduce the thickness variation of the ONO layer, thereby improving endurance and bake retention characteristics of the semiconductor device.

Method of forming a gate of a non-volatile memory device

A method of forming a gate structure of a semiconductor device includes forming a gate insulation film and a polysilicon film on a semiconductor substrate where an active region and a field region are defined, followed by forming a buffer layer on the polysilicon film to minimize damage to the polysilicon film during a subsequent ion implantation process. The polysilicon film is made electrically conductive by the implanting of impurities into the polysilicon film. Gate patterns are then formed by etching the conductive polysilicon film and the gate insulation film. Defects, such as active pitting, associated with dual electrodes are effectively prevented because the polysilicon film is protected during the ion implanting process.

Method of forming gate electrode structure of a semiconductor device

Disclosed is a method of manufacturing a MOS transistor having an enhanced reliability. A passivation layer is formed on a gate electrode and on a substrate to prevent a generation of a recess on the substrate. After a mask pattern is formed on the substrate for masking a portion of the substrate, impurities are implanted into an exposed portion of the substrate to form source and drain regions. The substrate is rinsed so that the passivation layer or a recess-prevention layer is substantially entirely or partially removed while the mask pattern is substantially completely removed, thereby forming the MOS transistor. Therefore, the generation of the recess in the source and drain region of the substrate can be prevented due to the passivation layer during rinsing of the substrate.

Method of manufacturing a metal oxide semiconductor transistor

Growing community of inventors

Incheon, South Korea

Bong-hyun Kim