Samsung Electronics Co., Ltd.

Bong-Hyun Choi

Seung-Jun Shin

Jin-Ho Kim

Joon-Sung Lim

Jae-Hwang Sim

Jong-Mil Youn

Min-Sung Song

Jin-hyun Shin

Si-Wan Kim

A vertical memory device includes a substrate including a cell array region and a staircase region surrounding the cell array region, gate electrodes on the cell array region and the staircase region, and a channel on the cell array region. The gate electrodes are isolated from each other in first and third directions and each extend in a second direction. The channel extends in the first direction through one or more gate electrodes. End portions in the second direction of first gate electrodes of the plurality of gate electrodes define first steps in the second direction and second steps in the third direction on the staircase region of the substrate, the second steps being connected to the first steps, respectively, at same levels.

Vertical memory devices

A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.

In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask.

Method of manufacturing semiconductor device

Ternary CAM cells are provided. The ternary CAM cell includes a pair of half cells. Each of the half cells includes an isolation layer formed at a predetermined region of a semiconductor substrate to define a match cell active region. A search gate electrode and a node gate electrode are placed to cross over the match cell active region. A match line is electrically connected to the match cell active region, which is adjacent to the node gate electrode and is located opposite the search gate electrode. An SRAM cell is provided at the semiconductor substrate adjacent to the match cell active region. The node gate electrode is electrically connected to one of a pair of storage nodes of the SRAM cell.

Growing community of inventors

Yongin-si, South Korea

Bong-Hyun Choi