Hynix Semiconductor Inc.

Skhynix Inc.

Bong-Hwa Jeong

Jin-Hong Ahn

Saeng-Hwan Kim

Shin-Ho Chu

Tae-Jin Kang

Chang-Hyun Lee

Jae-Boum Park

Young-Chul Sohn

A semiconductor device may include a trimming circuit suitable for generating a reference voltage that is adjusted based on a code value, and an internal voltage generation circuit suitable for generating an internal voltage based on the reference voltage, wherein the internal voltage generation circuit is suitable for dividing the internal voltage in a division ratio that varies depending on an operation mode and for generating the internal voltage based on comparison of the divided internal voltage with the reference voltage.

Semiconductor device and internal voltage adjusting method thereof

A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

Self refresh operation of semiconductor memory device

A semiconductor memory apparatus includes: a compensation voltage input node; a core voltage generator configured to generate a core voltage using an external power source voltage and supply the core voltage to the compensation voltage input node; a compensation controlling unit configured to generate a compensation control signal to determine power compensation, in response to a refresh signal; a power compensating unit configured to selectively supply the external power source voltage to the compensation voltage input node in response to the compensation control signal; and a power supply unit configured to supply a voltage at the compensation voltage input node or the external power source voltage to a sense-amp driver in response to a first power control signal or a second power control signal.

Semiconductor memory apparatus

An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.

Apparatus and method for data outputting

A circuit for supplying power to a sense amplifier in a semiconductor memory apparatus includes: a compensation controlling unit configured to generate a compensation control signal to determine power compensation, in response to a refresh signal. A power compensating unit supplies a compensation voltage input node, which is applied with a first voltage, with a second voltage in response to the compensation control signal. And, a power supply unit configured to supply the second voltage or a voltage at the compensation voltage input node to a sense-amp driver in response to a first power control signal or a second power control signal.

Circuit and method for supplying power to sense amplifier in semiconductor memory apparatus

An internal voltage supply circuit may Include a first internal voltage generator for receiving an external voltage and generating a first internal voltage, a second internal voltage generator for generating a second internal voltage lower than the first internal voltage, and a switching circuit responsive to a control signal, for supplying the second internal voltage to a refresh-associated circuit in a refresh mode and the first internal voltage to the refresh-associated circuit in normal mode. The control signal is enabled in the refresh mode.

Internal voltage supply circuit of a semiconductor memory device with a refresh mode

An internal voltage generator for generating a back bias voltage includes a back bias voltage pumping block for comparing a reference voltage with a feedback back bias voltage to generate a back bias enable signal and the back bias voltage in response to an activated self refresh signal and a back bias voltage discharge controlling unit for discharging the back bias voltage into a ground voltage in response to the activated self refresh signal and the back bias enable signal.

Back-bias voltage generator for decreasing a current consumption of a self-refresh operation

The present invention provides a semiconductor memory device capable of being stably operated by reducing power noise generated while a sense amplifier performing for sensing and amplifying data supplied to a bit line. For this object, an inventive semiconductor memory device includes a cell array having a plurality of cells; a plurality of bit lines supplied with voltage stored in the plurality of the cells; a plurality of sense amplifier block for sensing and amplifying a voltage of the plurality of the bit lines, each bit line being connected to each cell; a plurality of switches for selectively connecting or disconnecting the plurality of the sense amplifier block to the plurality of the bit lines; and a sense amplifier control block for turning on the plurality of the switches by using at least two different timing sets.

Semiconductor memory device reducing noise

A current reducing device is provided in a sense amplifier over driver scheme of a semiconductor memory chip. The device can reduce the amount of the electric current consumed unnecessarily during the discharging operation by differing the reference voltages of a cell power voltage discharge unit and a cell power voltage generation unit during a portion of a discharging period.

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Kyoungki-do, South Korea

Bong-Hwa Jeong