Samsung Electronics Co., Ltd.

Optomind Inc.

Korea Advanced Institute of Science and Technology

Mitsubishi Gas Chemical Company, Inc.

Bong-cheol Kim

Dae-youp Lee

Yung-sung Son

Byeong-hwan Son

Jae-Han Lee

Hyun-Woo Kim

Dong-Seok Lee

Kwang-sub Yoon

Jung-hyeon Lee

Eun-sung Kim

Young-Moon Choi

Sang-shin Lee

Sang-youn Jo

Jong-su Park

Yong Geon Lee

Se-Young Park

Yong-Geon Lee

Chun-taek Rim

Eun-soo Lee

Byeong-Hwan Son

Sang-sin Lee

Ja-min Koo

Jang-hwan Jeong

Eun-Shoo Han

Bo-hwan Choi

Yung-Sung Son

Embodiments of the present disclosure provide an optical assembly for high speed optical communications by combining a cover assembly including a lens and a cover post with a body assembly including a lens, reflection prism and body hole, which takes only a few passive optical alignments for providing aligned optical elements that have required multiple complex and sophisticated processes.

Optical assembly for light transmission and reception

Embodiments according to the present disclosure relate to an optical transmitting device and an optical receiving device which can minimize the alignment error between the light source and the photodetector on the substrate, miniaturize the devices, and require no separate guide member reducing manufacturing costs, while satisfying the design requirements for sub-miniaturization, and performing optical transmission and reception more efficiently.

Optical transmitting device including first lens and reflector mounted to housing body and second lens mounted to housing cover

An optical transceiver device includes a baseplate including a set position for mounting an optical element, an alignment plate including a mounting unit, a first and a second reference hole. The device includes an optical-fiber fixing block configured to fixedly mount at least one of a lens unit and an optical fiber optically linked with the optical element and to include a first and a second post, and a housing for enclosing the optical-fiber fixing block and alignment plate. The second post is inserted into the second reference hole in a looser manner than inserting the first post into the first reference hole, and the set position is determined by a first baseline passing through the first and the second reference hole and by a second baseline intersecting with the first baseline and positioned on opposite side of the second reference hole with respect to the first reference hole.

Optical transceiver device

A method for fabricating a semiconductor device is provided, which includes forming a first mask pattern and a second mask pattern on a first layer, forming a block mask that covers the second mask pattern on the first layer, forming first spacers on side walls of the first mask pattern, exposing the second mask pattern through removal of the first mask pattern and the block mask, forming a third mask pattern and a fourth mask pattern through etching of the first layer using the first spacers and the second mask pattern as etch masks, and forming second spacers and third spacers on side walls of the third mask pattern and side walls of the fourth mask pattern, respectively.

Method for fabricating semiconductor device

A structure for aligning an optical element includes a baseplate including a set position for mounting at least one optical element, a first reference hole, and a second reference hole spaced by a first distance from the first reference hole. The set position is determined by a first baseline that passes the first reference hole and the second reference hole and a second baseline that intersects with the first baseline at a second distance from the first reference hole on an opposite side to the second reference hole with respect to the first reference hole. The second distance is shorter than the first distance.

Method and apparatus for aligning optical element

The present disclosure provides an AC-direct-type LED-lighting device including compensation circuit for AC input compensation, including a compensation inductor and first compensation capacitor parallelly connected to one terminal of AC input and a second compensation capacitor connected in series; rectifying unit for rectifying output from second compensation capacitor terminals to obtain direct current; and LED array driven by the rectifying unit output, wherein capacities of the first and second compensation capacitors and the compensation inductor and LED array output voltage are determined to cause 0.9 or larger cosine value of a phase, with respect to the AC input voltage, of resulting current obtained by dividing AC input voltage by sum of (i) parallel value of an equivalent impedance Rof the rectifying unit and LED array and an impedance of the second compensation capacitor and (ii) parallel value of impedances of the compensation inductor and first compensation capacitor.

Parallel-type LED lighting device

Metal contacts are formed within a string overhead area using a double patterning technology (DPT) process thereby allowing for the reduction of a string overhead area and a concomitant reduction in the chip size of a semiconductor device. A first mask pattern is formed by etching a first mask layer, the first mask pattern including a first opening formed in a cell region and a first hole formed in a peripheral region. A first sacrificial pattern is formed on the first mask pattern and the exposed first insulating layer of the cell region using a double patterning technology process. Contact holes are formed by exposing the target layer by etching the first insulating layer using the first mask pattern and the first sacrificial pattern as an etch mask. Metal contacts are then formed in the contact holes.

Method of fabricating metal contact using double patterning technology and device formed thereby

Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern. First spacers covering side walls of the first mask pattern and second spacers covering side walls of the second mask pattern are formed. The first mask pattern is removed, and then the substrate is etched in the first region and the second region by using the first spacers as an etch mask in the first region, and the second mask pattern and the second spacers as an etch mask in the second region.

Methods of forming patterns for semiconductor devices

Provided is a photomask used in fabrication of a semiconductor device. The photomask includes first and second regions to be transferred onto a semiconductor substrate having a step difference. The first and second regions have mask patterns. The mask patterns of the first region have a different shape from the mask patterns of the second region. The mask patterns of the second region have concave and convex portions disposed in opposite lateral portions thereof.

Photomask used in fabrication of semiconductor device

Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask.

Method of forming semiconductor device patterns

In a method of manufacturing a capacitor and a method of manufacturing a dynamic random access memory device, an insulating layer covering an upper portion of a conductive layer may be provided with an ozone gas so as to change the property of the upper portion of the insulating layer. The upper portion of the insulating layer may be chemically removed to expose the upper portion of the conductive layer. The exposed upper portion of the conductive layer may be removed so as to transform the conductive layer into a lower electrode. The remaining portion of the insulating layer may be removed, and an upper electrode may be formed on the lower electrode.

Growing community of inventors

Seoul, South Korea

Bong-cheol Kim