Samsung Electronics Co., Ltd.

Bon-Young Koo

Chul-Sung Kim

Byeong-Chan Lee

Jin-bum Kim

Yong-Suk Tak

Ki-Yeon Park

Su-Jin Jung

Ki-Hyun Hwang

Sung-Hyun Choi

Gi-Gwan Park

Tae-Jong Lee

Seok-hoon Kim

Young-Jin Noh

Kwan-heum Lee

Seok-Hoon Kim

Young-jin Noh

Sung-Kweon Baek

Si-Young Choi

Yu-Gyun Shin

Gyeom Kim

Nam-Kyu Kim

Jung-Geun Jee

Cho-eun Lee

Woo-bin Song

Jin-Hee Han

Sung-kweon Baek

Chul Kyu Kim

Woong Hee Lee

Jin-Gyun Kim

Hun-Hyeoung Leam

Kyung-In Choi

Hong-Sik Yoon

Ki-hyun Hwang

Wook-Je Kim

Jin-Hwa Heo

Chang-Won Choi

Jae-young Park

Seok-woo Nam

Jin-yeong Joe

Deok-han Bae

Hyun-ho Noh

Won-Oh Seo

Chang-Hyun Lee

Bo-un Yoon

Ji-Hyun Kim

Sun-Young Lee

Dong-Hun Lee

Han-jin Lim

Young-Pil Kim

Ji-Hoon Cha

Jae-Jik Baek

Jae-Jong Han

Taek-Soo Jeon

Sug-hun Hong

Sang-jin Hyun

Dong-Chan Suh

Jeong-Do Ryu

Jin-Tae Noh

Sang-Ryol Yang

Tae-Ouk Kwon

Jeong-ho Yoo

Kang-Hun Moon

Nam Kyu Kim

Han-ki Lee

Hyun-seung Kim

Young-Sub Yu

Kwan-Heum Lee

Yong-Kook Park

Jin-Bum Kim

Cho-Eun Lee

Mi-seon Park

A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

Semiconductor device with adjacent source/drain regions connected by a semiconductor bridge, and method for fabricating the same

A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.

Semiconductor devices and methods of manufacturing the same

A material layer, a semiconductor device including the material layer, and methods of forming the material layer and the semiconductor device are provided herein. A method of forming a SiOCN material layer may include supplying a silicon source onto a substrate, supplying a carbon source onto the substrate, supplying an oxygen source onto the substrate, supplying a nitrogen source onto the substrate, and supplying hydrogen onto the substrate. When a material layer is formed according to a method of the present inventive concepts, a material layer having a high tolerance to wet etching and/or good electric characteristics may be formed, and may even be formed when the method is performed at a low temperature.

Material layers, semiconductor devices including the same, and methods of fabricating material layers and semiconductor devices

A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.

Methods of fabricating a SiOCN layer using a first and second carbon precursor, the first carbon precursor being different from the second carbon precursor

A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

Semiconductor device and method of fabricating the same

A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.

Semiconductor devices having bridge layer and methods of manufacturing the same

A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

Methods of manufacturing semiconductor devices including gate pattern, multi-channel active pattern and diffusion layer

An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer structure.

Integrated circuit device and method of manufacturing the same

A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked.

Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.

Semiconductor devices

A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.

Integrated circuit device and method of fabricating the same

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a multi-channel active pattern including germanium and an inner region and an outer region, the outer region formed along a profile of the inner region, and a germanium fraction of the outer region being smaller than a germanium fraction of the inner region. A gate electrode intersects the multi-channel active pattern.

A semiconductor device may have a structure that prevents or reduces an etching amount of certain portions, such as a part of a source/drain region. Adjacent active fins may be merged with a blocking layer extending between adjacent the source/drain region. The blocking layer may be of a material that is relatively high-resistant to the etchant.

Semiconductor device and method for fabricating the same

Growing community of inventors

Suwon-si, South Korea

Bon-Young Koo