Samsung Electronics Co., Ltd.

Bok-Moon Kang

Seung-Moon Yoo

Jei-Hwan Yoo

An internal power supply circuit for a semiconductor memory device comprising a differential amplifier having a reference voltage as an input and utilizing an external power supply voltage. An amplifier output provides an internal power supply voltage. The amplifier is connected to a current source which comprises a plurality of transistors connected in series between one side of said amplifier and ground. A current control transistor having a channel larger than the channels of the transistors connected in series is switchable between a first state in which the current control transistor is substantially on and a second state in which said current control transistor is substantially off.

Source voltage generating circuit in semiconductor memory

A data in/out channel control circuit for a semiconductor memory device with multi-bank structure includes a plurality of split banks each provided with memory cell arrays, each split bank having a plurality of bit line pairs and a sub in/out line pair connected through a column selection transistor pair, for efficiently connecting data from the bit line pairs to a global in/out line pair. The circuit enables transmission of only the data in a given block bank through the global in/out line pair and the sub in/out line pairs with bank selection information and block selection information. The circuit includes a pair of global in/out lines, global column selection lines extending in a direction of the bit line pair, a column decoding means for activation of any one of the global column selection lines responsive to a decoding of the column selection information, local column selection lines connected to each gate of the column selection transistors, means for generating a bank selection signal for selecting at least one of the plurality of banks by decoding column selection information and row selection information, and a switching means for connecting the sub in/out line pair of the corresponding bank to the global in/out line pair as well as connecting the global column selection line to the local column selection line of the bank in response to the bank selection signal.

Data in/out channel control circuit of semiconductor memory device

An address buffer for a semiconductor memory device having an address input buffer and an address predecoder incorporated together so as to be driven in a single channel, capable of reducing an address predecoding time by a logic combination of outputs of address input buffer, for high speed of operation of a memory device. The address buffer is provided with one or more address input means connected between a power supply voltage and a ground voltage, for amplifying a given number of addresses received from an external device to thereby provide a stable level of outputs in response to an address input enable signal, a delay circuit having inputs connected with the outputs of said address input means, for converting the outputs of said address input means into a stable logic level and delaying the outputs by a given time interval for a delivery in conformity with the addressing time, an address predecoder connected with the outputs of said delay circuit, for providing a decoded address according to a predetermined logic combination of the outputs of said delay circuit, a transmission latch circuit coupled to said address predecoder, for transmitting and latching the decoded address from said address predecoder in accordance with an address latch signal, and an output driver coupled to said transmission latch circuit, for driving the decoded address output from said transmission latch circuit in a stable level for a delivery to a memory cell.

Address buffer for high-speed address inputting

A substrate bias voltage controlling circuit controls the generation of different substrate bias voltages according to specific modes. A first sensing signal generator is controlled by the substrate bias voltage and generates a first sensing signal when the level of the substrate bias voltage is higher than a predetermined first potential level. A second sensing signal generator is controlled by the substrate bias voltage and a specific mode signal and generates a second sensing signal when the level of the substrate bias voltage is higher than a predetermined second potential level and when the mode signal is enabled.

Substrate bias voltage controlling circuit in semiconductor memory device

A low power semiconductor memory device for minimizing power consumption is disclosed. The low power semiconductor memory device includes a memory cell array with a plurality of memory cells connected to a pair of bit lines, and having first and second pairs of data lines each having a normal data line and a complementary data line. The device further includes a first switching circuit for switch-connecting the pair of bit lines to the first pair of data lines in response to column select information and a sense amplifier connected to the pair of bit lines within the memory cell array. A driving circuit transfers external data to one of the normal data line and the complementary data line of the second pair of data lines in response to a write master signal. A data transfer circuit respectively transfers a signal of the normal data line of the second pair of data lines and an inverted signal thereof to the normal data line and the complementary data line of the first pair of data lines in response to the input of the write master signal.

Low power semiconductor memory device

Disclosed is a DC voltage generating circuit for reducing an electric power consumption in a semiconductor memory device. The DC voltage generating circuit comprises: a refresh counter for setting a refresh cycle; a power source supply controller for logically combining a counting value supplied from the refresh counter and a self-refresh timer driving signal, thereby to generate a power source supply control signal in a refresh section; and a DC voltage generator for generating and supplying a DC voltage through an output terminal of the DC voltage generator, as controlled by the power source supply control signal supplied from the power source supply controller.

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Suwon, South Korea

Bok-Moon Kang