Qualcomm Incorporated

Rambus Inc.

Bohuslav Rychlik

Andrew Edmund Turner

Sumit Sur

George Patsilaras

Steven S Thomson

Ali Iranli

Liang Leon Peng

Thomas J Sheffler

Lawrence Lai

Feng Wang

Brian J Salsbery

Moinul H Khan

Wesley James Holland

Norman S Gargash

Anwar Q Rohillah

Steven Cameron Woo

Jon James Anderson

Hee Jun Park

Craig Edward Hampel

Dexter Tamio Chun

Matthew Levi Severson

Subrato Kumar De

Jaya Prakash Subramaniam Ganasan

Qi Lin

Serag Gadelrab

Richard Alan Stewart

Gheorghe Calin Cascaval

Li Feng Zhang

Rajarshi Gupta

John Eric Linstadt

Andrew Evan Gruber

Brent Steven Haukness

James Norris Dieffenderfer

Vinay Sridhara

Thomas Andrew Sartorius

Kun Xu

Yanru Li

Michael W Morrow

Christopher E Koob

Jason Edward Podaima

Simon Peter William Booth

Paul Christopher John Wiercienski

Jeffrey Shabel

Jeffrey Gemar

Kyle Ernewein

Jeffrey A Niemann

James Michael Artmeier

Philip T Mueller, Jr

Simon Booth

Babak Salamat

Carlos Javier Moreira

Mehrdad Mohammad H Reshadi

Kris Tiri

Mark D Guzzi

Engin Ipek

Mark S Fowler

Andrey Ermolinskiy

Manokanthan Somasundaram

Robert A Glenn

Alexei Vladimirovich Bourd

Chinh Viet Tran

Prajakt Kulkarni

Mark Michael Schaffer

Meghal Varia

Thomas Zeng

Colin Christopher Sharp

Subbarao Palacharla

Dipti Ranjan Pal

Rashmi Kulkarni

Joshua Stubbs

Vinod Chamarty

Eric Demers

Madan Krishnappa

Steven Halter

Hao Liu

Liang Peng

Jeffrey Hao Chu

Huang Huang

Cristian Duroiu

Songhe Cai

Ling Feng Huang

Edoardo Regini

Christophe Avoinne

Alexander Miretsky

Robert Nicholson Gibson

Satish Anand

Tzung Ren Tzeng

Sina Dena

Chih-Chi Cheng

Jeong-Ho Woo

Tarek Zghal

Serag Monier GadelRab

Farrukh Hijaz

Myil Ramkumar

Alan Young

William Bainbridge

Raymond P Palma

Fahad Ali

Can Hankendi

Thomas A Sheffler

A memory device having a DRAM core and a register stores first data in the register before receiving first and second memory access commands via a command interface and before receiving second data via a data interface. The memory device responds to the first memory access command by writing the first data from the register to the DRAM core and responds to the second memory access command by writing the second data from the data interface to the DRAM core.

Command-differentiated storage of internally and externally sourced data

Providing content-aware cache replacement and insertion policies in processor-based devices is disclosed. In some aspects, a processor-based device comprises a cache memory device and a cache controller circuit of the cache memory device. The cache controller circuit is configured to determine a plurality of content costs for each of a plurality of cached data values in the cache memory device, based on a plurality of bit values of each of the plurality of cached data values. The cache controller circuit is configured to identify, based on the plurality of content costs, a cached data value of the plurality of cached data values associated with a lowest content cost as a target cached data value. The cache controller circuit is also configured to evict the target cached data value from the cache memory device.

Providing content-aware cache replacement and insertion policies in processor-based devices

Certain aspects of the present disclosure provide techniques for improved hardware utilization. An input data tensor is divided into a first plurality of sub-tensors, and a plurality of logical sub-arrays in a physical multiply-and-accumulate (MAC) array is identified. For each respective sub-tensor of the first plurality of sub-tensors, the respective sub-tensor is mapped to a respective logical sub-array of the plurality of logical sub-arrays, and the respective sub-tensor is processed using the respective logical sub-array.

Allocation of data sub-tensors onto hardware sub-arrays

A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

Data write from pre-programmed register

DRAM with command-differentiated storage of internally and externally sourced data

Various embodiments include methods and devices for virtual cache coherency. Embodiments may include receiving a snoop for a physical address from a coherent processing device, determining whether an entry for the physical address corresponding to a virtual address in a virtual cache exists in a snoop filter, and sending a cache coherency operation to the virtual cache in response to determining that the entry exists in the snoop filter.

Space and time cache coherency

The energy consumed by data transfer in a computing device may be reduced by transferring data that has been encoded in a manner that reduces the number of one '1' data values, the number of signal level transitions, or both. A data destination component of the computing device may receive data encoded in such a manner from a data source component of the computing device over a data communication interconnect, such as an off-chip interconnect. The data may be encoded using minimum Hamming weight encoding, which reduces the number of one '1' data values. The received data may be decoded using minimum Hamming weight decoding. For other computing devices, the data may be encoded using maximum Hamming weight encoding, which increases the number of one &#x201c;1&#x201d; data values while reducing the number of zero &#x201c;0&#x201d; values, if reducing the number of zero values reduces energy consumption.

Data re-encoding for energy-efficient data transfer in a computing device

In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

Multi-stage biometric authentication

Memory component that performs data write from pre-programmed register

In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

System and method for mixed tile-aware and tile-unaware traffic through a tile-based address aperture

An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

System and method for intelligent tile-based prefetching of image frames in a system on a chip

Systems and methods enable displaying a graphical representation of system resource usage in a resource utilization map to inform users about system resource utilization by applications and processes running on a computing device. Users may provide inputs to enable the system to adjust resource allocations based on user preferences. This may enable users to improve the overall operational performance of the device consistent with their current personal preferences by identifying applications or processes of most or least interest so the device processor to prioritize system resources accordingly. Some aspects transmit resource allocation data based on such user input to a central server to enable community based resource allocation schemes. Community based resource allocation schemes may be transmitted to computing devices for use as default or preliminary resource allocations for particular applications, websites or device operating states.

Method and apparatus for optimized execution using resource utilization maps

Single command, multiple column-operation memory device

Systems and methods for managing coherency in a processing system comprising a memory involve one or more aperture cache coherency (ACC) blocks. The ACC blocks monitor accesses to the memory using aliased addresses, wherein the aliased addresses map to locations in an aliased address domain of the memory. The ACC blocks also monitor accesses to the memory through a functional address aperture using aperture addresses, wherein a function of the aperture addresses map to locations in an aperture address domain of the memory. The ACC blocks are further configured to maintain coherency between one or more of data in a first location of the memory, the first location belonging to the aliased address domain and the aperture address domain; one or more copies of the data accessed using the aperture addresses; or one or more copies of the data accessed using the aliased addresses.

Cache coherence with functional address apertures

Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks

Growing community of inventors

San Diego, CA, United States of America

Bohuslav Rychlik