Signetics

Bohumil Polata

Vittorio De Nora

James A Marley, Jr

Defect formations and unwanted in diffusions caused by residual impurity products is prevented in a semiconductor fabrication method which includes the step of forming a composite mask which simultaneously defines base, collector and diffusion isolation openings. After these openings are defined a thin protective layer of silicon dioxide is grown over the exposed area and remains there throughout the remainder of the doping process which includes the steps of selectively covering areas which are not to be doped with photoresist and thereafter ashering the photoresist to remove it in preparation for the next ion implantation step. The thin protective layer of silicon dioxide protects nonselected areas against residual impurity products formed during removal of the photoresist.

Method for fabricating semiconductor devices utilizing oxide protective

Single bipolar transistor memory cell in which information is stored on the collector to substrate capacitance. This capacitance may be enhanced by an additional diffused region. Storage and retrieval of information is accomplished through only two leads connected to the transistor which is operated so that a portion of the base is fully depleted during a portion of the operating memory cycle of the memory cell.

Single bipolar transistor memory cell and method

The buried layer of an integrated circuit is produced by use of a grated mask. The growth of silicon dioxide in the exposed areas of the grate forms a stepped surface. Thereafter ion implantation in these areas and then merging the implanted regions forms a single buried region having a corrugated surface on which an epitaxial layer is grown. Such corrugated surface reduces the defect regions in the epitaxial layer.

Method for reducing the defect density of an integrated circuit

A majority charge carrier semiconductor structure including a relatively heavily doped n type support layer, a second n type layer formed on the support layer and having a relatively light doping, a p layer formed on the second n layer, and a third n type layer having a relatively heavy doping formed atop the p layer. When voltage means is applied between top and support layers principal current flow is by majority charge carriers in either direction determined by the polarity of a pre-determined voltage. Current flow occurs substantially below the critical electric field, and free of avalanche multiplication or tunneling. In alternate embodiments the doping impurity concentration may be varied to alternately provide a device wherein the magnitude of voltage reference which determines current flow in one direction or in the opposite direction may be symmetrical, asymmetrical or highly asymmetrical.

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Los Altos, CA, United States of America

Bohumil Polata