Atmel Corporation

Bohumil Lojek

Alan L Renninger

Michael D Whiteman

Eleonore Daemen

A method of non-thermal annealing of a silicon wafer comprising irradiating a doped silicon wafer with electromagnetic radiation in a wavelength or frequency range coinciding with lattice phonon frequencies of the doped semiconductor material. The wafer is annealed in an apparatus including a cavity and a radiation source of a wavelength ranging from 10-25 &#x3bc;m and more particularly 15-18 &#x3bc;m, or a frequency ranging from 12-30 THz and more particularly 16.5-20 THz.

Non-thermally annealed doped semiconductor material and methods related thereto

An EEPROM having a charge storage element, i.e., a floating gate, in the substrate adjacent to vertically separated source and drain electrodes. An electrically transparent poly control gate allows relatively low voltages to be used for program, erase, and read operations when a plurality of similar devices are arranged in a memory array. A second poly member, called a tunnel poly member, communicates with source and drain electrodes in synchronism with the poly control gate to provide charge carriers to the floating gate. Manufacturing involves a series of layers with minimal needs for photolithography.

Low voltage non-volatile memory cell with electrically transparent control gate

An array of memory cells with non-volatile memory transistors having a compact arrangement of diagonally symmetric floating gates. The floating gates have portions extending in both X and Y directions, allowing them to be charged through a common tunnel oxide stripe that runs under a portion of each, for example a portion running in the X-direction while the two Y-direction portions serve to establish a channel. Shared source/drain regions are established between and in proximity to the Y-direction portions to define two non-volatile memory transistors in each memory cell. Memory cells are replicated in the word line direction and then mirrored with respect to the word line to form the next row or column. This geometry is contactless because the word line and source/drain regions are all linear throughout the array so that electrical contact can be established outside of the array of cells. Each transistor can be addressed and thus programmed and erased or pairs of transistors in a line can be erased, i.e., sector erase.

Contactless nonvolatile memory array

Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Self-aligned non-volatile memory cell

A method of simultaneously fabricating at least two semiconductor devices, at least bone of which is a nanocrystal memory and at least one of which is a non-nanocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semiconductor devices being fabricated. The nanocrystal layer is removed from at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated. A polycrystalline gate is formed for each of the semiconductor devices being fabricated. Doping is provided to provide the source and drain regions for each of the semiconductor devices being fabricated. The substrate is thermally treated after the doping. The thermal budget of the fabrication process is not limited by this thermal treatment.

Method for simultaneous fabrication of a nanocrystal and non-nanocrystal device

A pair of nonvolatile memory transistors are carved from a single polysilicon floating gate on an insulated substrate. After surrounding the poly floating gate with insulator, the poly is etched except for two remnants remaining on lateral sides of the original floating gate. These remnants become a pair of new floating gates for the transistor pair. Prior to etching of the poly, the poly may be used for self-aligned placement of highly doped regions that serve as electrodes for the two transistors. If the single poly floating gate has a minimum feature size for a manufacturing process, the pair of poly remnants remaining after etching are even smaller, perhaps less than a fraction of the minimum feature size. With this small size, the devices will operate by band-to-band tunneling, i.e. without tunnel oxide, characteristic of larger EEPROM and EPROM devices. A single conductive control electrode over the poly remnants can allow both transistors to operate as independent storage devices if bit lines, connected to other electrodes, are phased.

Method of making nonvolatile transistor pairs with shared control gate

A block alterable memory cell has a select control gate extending from a floating gate region to a drain region. The block alterable memory cell comprises a substrate layer that further includes a source implant region, a floating gate transistor region, and a drain implant region. A tunnel oxide layer overlies the substrate layer and is deposited to a thickness of approximately 70 angstroms. A first oxide layer overlies the tunnel oxide layer, with an inter poly layer overlying the first oxide layer, and a second poly layer extending over the floating gate transistor region to an edge of the drain implant region.

Method of making EEPROM transistor pairs for block alterable memory

A field effect transistor (FET) device structure and method for forming FETs for scaled semiconductor devices. Specifically, FinFET devices are fabricated from silicon-on-insulator (SOI) wafers in a highly uniform and reproducible manner. The method facilitates formation of FinFET devices with improved and reproducible fin height control while providing isolation between source and drain regions of the FinFET device.

Self-aligned nanometer-level transistor defined without lithography

Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric 'boot shape' on a lower edge of the dielectric separation layer. An area within this non-photolithographically produced boot region defines an emitter contact window. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region. Feature sizes are determined by deposition and etching techniques. Consequently, photolithography of small features is eliminated.

Method of fabricating a semiconductor device having a toroidal-like junction

A doped silicon block or island, formed above a drain electrode in substrate of a die or chip, has a height corresponding to the desired length of a channel. A source electrode is formed above the silicon island and allows for contact from above. Contact from above may also be made with an L-shaped control gate and with the subsurface drain. A horizontal array of contacts for source, gate and drain is formed for the vertical transistor that is built. If a layer of nanocrystals is incorporated into a layer between the gate and the channel, a non-volatile floating gate transistor may be formed. Without the layer of nanocrystals, an MOS or CMOS transistor is formed.

Ultrascalable vertical MOS transistor with planar contacts

A non-volatile transistor memory array has individual cells with a current injector and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated by a word line, the active row has current injectors ready to operate if program line voltages are appropriate to cause charge storage in a memory cell, while a cell in an adjacent row be erased by charge being driven from a memory transistor. A series of conductive plates are arranged over the word line, with each plate having a pair of oppositely extending tangs, one causing programming of a cell in a first row and another causing erasing of a cell in another row.

Non-volatile memory array with simultaneous write and erase feature

A low voltage non-volatile charge storage transistor has a nanocrystal layer for permanently storing charge until erased. A subsurface charge injector generates secondary carriers by stimulating electron-hole current flowing toward the substrate, with some carriers impacting charge in nanocrystals. The charge injector is a p-n junction diode where one polarity is source and drain electrodes and the other polarity is two split doped regions in the substrate partially overlapping the active area on opposite sides of the active area. Any misalignment of masks for making the injected doped portions is inconsequential because a misalignment on one side of the active area offsets the corresponding misalignment on the other side. The injector implanted portions with overlap in the active area always have the same total area in the active area. This leads to programming reliability.

Non-volatile nanocrystal memory transistors using low voltage impact ionization

A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers which allows a tunnel window of a storage device to be fabricated in close proximity to an associated select gate and with a reduced gate width compared to typical devices. The tunnel window is recessed within an upper surface of a substrate. The tunnel window recess is made possible by selective etching of the substrate and oxides covering the substrate. A substantial reduction in the size of a tunnel window means device scaling is possible far beyond what is attainable with standard photolithography. Standby current is reduced significantly by fabricating a select device with complementary material types for the gate compared with the adjacent source/drain regions.

Memory cell with reduced size and standby current

Semiconductor device with a toroidal-like junction

A method of simultaneously fabricating at least two semiconductor devices, at least one of which is a nanocrystal memory and at least one of which is a non-nonocrystal semiconductor device. A nanocrystal layer is formed over an oxide layer of the at least two semiconductor devices being fabricated. The nanocrystal layer is removed from at least one portion of the substrate corresponding to the at least one non-nanocrystal device being fabricated. A polycrystalline gate is formed for each of the semiconductor devices being fabricated. Doping is provided to provide the source and drain regions for each of the semiconductor devices being fabricated. The substrate is thermally treated after the doping. The thermal budget of the fabrication process is not limited by this thermal treatment.

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Colorado Springs, CO, United States of America

Bohumil Lojek