Samsung Electronics Co., Ltd.

BoGeun Kim

Kitae Park

Eun-Jin Yun

Sangyong Yoon

Ohsuk Kwon

Youngsun Song

Seung-Hwan Shin

Doohyun Kim

Jinman Han

Yoon-Hee Choi

Yongkyu Lee

Chulho Lee

According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at least one operation condition based on the process capability index, and operating one of at least one nonvolatile memory device according to the at least one operation condition adjusted. The process capability index indicates how a structure associated with a memory cell to be operated deviates from a target shape.

Nonvolatile memory device and storage device having the same and operation method thereof

A storage device includes a variable resistance memory, a flash memory and a controller. The flash memory includes a plurality of memory cells connected to a plurality of word lines. The controller is configured to receive data from an external device and program the received data in the variable resistance memory or the flash memory according to a quantity of data to be programmed in the flash memory. Further, the controller is configured to read from the variable resistance memory and program the read data in the flash memory, when the quantity of data accumulated in the variable resistance memory corresponds to a super page of data.

Storage device including variable resistance memory, flash memory and controller

An operating method for a memory system including a nonvolatile random access memory (NVRAM) and a NAND flash memory includes performing a normal read operation directed to the target memory cell in response to a read request, determining that a read fail has occurred as a result of the normal read operation, then performing a read retry operation by iterations directed to the target memory cell according to a first read retry scheme until a pass read retry iteration successfully reads the target memory cell, and storing pass information associated with the pass read retry iteration in the NVRAM.

Operating method for memory system including nonvolatile RAM and NAND flash memory

An operating method is for a memory system which includes a NAND flash memory, a resistance variable memory, and a controller controlling the NAND flash memory and the resistance variable memory. The operating method includes receiving data, programming the received data in the NAND flash memory when the received data is at least a super page of data, programming the received data in the resistance variable memory when the received data is not a super page of data, and programming data accumulated in the resistance variable memory in the NAND flash memory when the accumulated data is a super page of data. A super page of data is an entirety of data that is programmable in memory cells connected to a same word line of the NAND flash memory.

Operating method of memory system including NAND flash memory, variable resistance memory and controller

A data programming method of a semiconductor memory device is provided which includes randomizing write data using a randomization method selected from among a plurality of randomization methods according to whether the write data is programmed in one of a plurality of nonvolatile memories; and programming the randomized write data in at least one of the plurality of nonvolatile memories, wherein the plurality of nonvolatile memories has different types from one another.

Semiconductor memory devices utilizing randomization and data programming methods thereof

A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Nonvolatile memory devices and methods of programming nonvolatile memory devices

A memory system including a first memory of a first type; a second memory of a second type; and a controller configured to control the first memory and the second memory. The first type and second type are different, and the controller is configured to control the first memory and the second memory according to substantially the same command sequence.

Memory system and operating method of controller

A memory device includes a plurality of memory cells serially connected between a bit line and a common source line and a plurality of word lines, respective ones of which are connected to respective gates of the plurality of memory cells. The memory device further includes a common source line compensation circuit configured to generate a compensated bias voltage on the bit line or at least one of the plurality of word lines responsive to a common source line voltage on the common source line. Related methods of operating memory devices are also provided.

Nonvolatile memory devices with common source line voltage compensation and methods of operating the same

A nonvolatile memory device and a programming method thereof perform a programming verification step including a selective verification step and a sequential verification step. In the selective verification step, a data input/output (I/O) circuit selectively precharges a selected bit line according to a temporary programmed state of stored data. In the sequential verification step, the data I/O circuit selectively precharges each bit line according to the result of the previous selective verification step or a previous sequential verification step. According to the programming method, because a memory cell not requiring a programming verification step is not precharged in the programming verification step, an ON cell current does not flow therethrough. Accordingly, the current flowing through a common source line during verification can be reduced.

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Suwon-si, South Korea

BoGeun Kim