Cypress Semiconductor Corporation

Infineon Technologies LLC

Longitude Flash Memory Solutions Ltd.

Bogdan I Georgescu

Ryan Tasuo Hirose

Igor G Kouznetsov

Vijay Raghavan

Cristinel Zonte

Sean B Mulholland

Leonard Vasile Gitlan

John J Silver

Fredrick B Jenne

Venkatraman Prabhakar

Iulian Constantin Gradinariu

Keith A Ford

Kaveh Shakeri

Paul Fredrick Ruths

James Paul Myers

Danny L Rose

Gary Peter Moscaluk

Ashish Ashok Amonkar

John W Tiede

Vijay Srinivasaraghavan

Timothy John Williams

Julian C Gradinariu

Antwerpen Hans Van

Gary P Mosculak

Ryan Hirose

A program operation targeted to a first page in a sector of non-volatile memory is identified. The sector includes an array of memory cells comprising a set of pages including the first page, and each page in the set of pages includes a set of tracking bits reserved for storing values of a freshness counter. A processing device determines a second page in the set of pages has been exposed to a maximum number of program operations in the set of pages based on a value of the freshness counter stored in the set of tracking bits of the second page. The maximum number of program operations is determined to exceed a program disturb threshold for the sector. The second page in the sector of non-volatile memory is refreshed in response to determining that the maximum number of program operations exceeds the program disturb threshold for the sector.

Techniques for managing program disturb in non-volatile memory

In accordance with an embodiment, a method for characterizing a non-volatile memory, includes: applying a first voltage on a word line conductively coupled to a non-volatile memory cell and measuring a current flowing through the non-volatile memory cell in response to applying the first voltage. Measuring the current includes: using a sense amplifier, comparing the current flowing through the non-volatile memory cell with a plurality of different first currents generated by an adjustable current source while applying the same first voltage on the word line, and determining the measured current based on the comparing.

System and method for testing a non-volatile memory

A method of erasing, during an erase operation, a non-volatile memory (NVM) cell of a memory device is disclosed. The erasing includes applying a first HV signal (VPOS) to a common source line (CSL). The CSL is shared among NVM cells of a sector of NVM cells. The first HV signal is above a highest voltage of a power supply. The erasing also includes applying the first HV signal to a local bit line (BL).

High voltage architecture for non-volatile memory

A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than Vis coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.

Method to reduce program disturbs in non-volatile memory cells

A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage note of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

Memory architecture having two independently controlled voltage pumps

A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.

A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

A biasing circuit includes cascoded transistors including a first transistor and a second transistor. A first gate of the first transistor is coupled to a second gate of the second transistor at a first node. The circuit also includes a voltage control circuit coupled to at least one of the first transistor or the second transistor. The voltage control circuit is configured to change a voltage level of at least one of the first transistor or the second transistor to allow voltage domain transition of an output signal in view of a change in state of an input signal without ramping a supply signal of the biasing circuit.

Negative high voltage hot switching circuit

A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.

High speed, high voltage tolerant circuits in flash path

Apparatus, systems, and methods for providing high voltage to memory devices are provided. One apparatus includes a low voltage input and a two-rail level shifting. The two-rail level shifting is configured to increase the low voltage or to decrease the low voltage to an amount that is less than or equal to a ground potential based on the amount of the low voltage. A system includes a low voltage input for receiving a voltage and a two-rail level shifting coupled to the low voltage input. The two-rail level shifting is configured to increase the voltage to a positive voltage if the voltage is equal to a ground potential and decrease the voltage to a negative voltage if the voltage is greater than the ground potential. One method includes receiving a voltage, modifying the voltage to generate one of a plurality of output voltages, and providing the output voltage to a memory device.

Systems and methods for providing high voltage to memory devices

Flash memory devices and systems are provided. One flash memory device includes an n-channel metal oxide semiconductor field-effect transistor (nMOSFET), a silicon-oxide-nitride-oxide silicon (SONOS) transistor coupled to the nMOSFET, and an isolated p-well coupled to the nMOSFET and the SONOS transistor. A flash memory system includes an array of memory devices divided into a plurality of paired sectors, a global bit line (GBL) configured to provide high voltage to each respective sector during erase and program operations coupled to each of the plurality of sectors, and a plurality of sense amplifiers coupled between a respective pair of sectors. Methods for operating a flash memory are also provided. One method includes providing high voltage, via the GBL, to the paired sectors during erase and program operations and providing low voltage, via a local bit line, to each memory device during read operations.

Growing community of inventors

Colorado Springs, CO, United States of America

Bogdan I Georgescu