Cadence Design Systems, Inc.

Microsoft Technology Licensing, LLC

Bogdan George Arsintescu

Donald John O'Riordan

Scott M Meyer

Gilles S C Lamant

Devendra Ramakant Deshpande

Balvinder Singh

Yan Yu

Brent D Miller

Ionut Constandache

Ian Campbell Dennison

Mark Baker

Alka Goel

The disclosed embodiments provide a system for performing unified error monitoring, alerting, and debugging of distributed systems. During operation, the system receives logs of activity within a distributed system over event streams in a distributed streaming platform. Upon identifying an error in the received logs, the system collects, from the event streams, log entries generated within a time window of the error into a contextual log associated with the error. The system then outputs an alert containing metadata for accessing the contextual log.

Unified error monitoring, alerting, and debugging of distributed systems

Various embodiments describe methods and systems for dynamic IP protection in electronic circuit designs. The methods or systems determine one or more levels of access or encryption and identify design data that should be made available for each level. For each level, a pcell instance is created to hide actual design data, and the design data that should be made available are moved to an instance of the corresponding sub-master in memory. The design data in this instance are encrypted in memory and are persisted in a side file in a non-volatile computer accessible storage medium. An authorized user is provided with a key, the side file, and a decrypting scheme to retrieve the actual design data with an appropriate level of details from the side file during a pcell evaluation process.

Methods, systems, and articles of manufacture for dynamic protection of intellectual property in electronic circuit designs

A method is provided to produce a persistent representation of a annotation to a circuit design comprising: providing a block hierarchy that corresponds to the circuit design; displaying in a computer user interface display a first elaborated view of the circuit design that corresponds to the first instance of a block hierarchy; receiving user input to associate the annotation with a component of the elaborated view of the design; providing in a mirrored block hierarchy; and associating the annotation with the mirrored block hierarchy in computer readable storage media.

Annotation management for hierarchical designs of integrated circuits

The present invention provides a system and method for generating circuit schematic that includes extracting connectivity data of a plurality of devices from a netlist, categorizing the plurality of devices into groups, placing Schematic Analog Placement Constraints on all the instances by identifying instances among the groups that match with a circuit template (in-built as well as user-specified), creating a BFS instance tree of tree instances, creating a two terminal device clusters and creating instance attachments. Using the constraints during grid based placement and eventually generated schematic which look like analog schematic.

System and method for circuit schematic generation

A computer-implemented method of identifying sub-circuits in circuit designs includes: receiving a selection of a sub-circuit; specifying a match expression for the sub-circuit, where the match expression characterizes matching properties of components of the sub-circuit; modifying the match expression to change the matching properties of components of the sub-circuit; and producing an information structure in a computer readable medium, where the information structure associates a graph representing a topology of the selected sub-circuit with the modified match expression. Subsequently, the information structure corresponding to the selected sub-circuit can be identified in a given circuit design.

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San Jose, CA, United States of America

Bogdan George Arsintescu