International Business Machines Corporation

Bogdan Cezar Zota

Kirsten Emilie Moselund

Nicolas J Loubet

Thomas E Morf

Marcel A Kossel

Pier Andrea Francese

Peter Mueller

Mridula Prathapan

Eunjung Cha

Katarzyna Hnida-Gut

Alan Molinari

Lorenzo Rocchino

Described is an integrated circuit device comprising one or more interconnects. Each interconnect of the one or more interconnects can be structured as a stack of layers including distinct topological layers, where each of the distinct topological layers can be a layer of topological material. Any two successive layers of the distinct topological layers can be separated by one or more interfaces, each forming a boundary between two consecutive layers of the stack, where the two consecutive layers can be engineered to preserve topologically protected surface states of each of the any two successive layers of the distinct topological layers.

Integrated circuit device with interconnects made of layered topological materials

A microelectronic structure including a bottom transistor having a gate region aligned along a first axis. An upper transistor located on top of the bottom transistor, where the upper transistor has a gate region that is aligned along a second axis, and where the second axis is perpendicular to the first axis.

SRAM with staggered stacked FET

One or more systems, devices and/or methods provided herein relate to a device that can facilitate generation of a pulse to affect a qubit and to a method that can facilitate fabrication of a semiconductor device. The semiconductor device can comprise an RTD and an FET co-integrated in a common layer extending along a substrate. A method for fabricating the semiconductor device can comprise applying, at a substrate layer, a template structure comprising an opening, a cavity and a seed structure comprising a seed material and a seed surface, and sequentially growing along the substrate a plurality of diode layers of an RTD and a plurality of transistor layers of an FET within the cavity of the template structure from the seed surface, wherein the RTD and FET are co-integrated along the substrate.

Co-integrated resonant tunneling diode and field effect transistor

Provided is a low noise amplifier circuit for a quantum computer. The low noise amplifier circuit comprises a plurality of input stages, a shared output stage, and a voltage controller. Each input stage is coupled to one or more qubits. The shared output stage is coupled to the plurality of input stages. The voltage controller is coupled to the plurality of input stages and the shared output stage. The voltage controller is configured to selectively activate an input stage of the plurality of input stages in order to read a qubit coupled to the input stage.

Parallelized low noise amplifiers for a quantum computer

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Rueschlikon, Switzerland

Bogdan Cezar Zota