Freescale Semiconductor,inc.

Bogdan Batog

Dragos Adrian Badea

Dragos Strada Valea Oltului Nr 12 Bl C9 ScB Ap 59 Badea

A software pipelining method for generating a schedule for executing a plurality of instructions on a processor, the plurality of instructions involving one or more variables, the processor having one or more physical registers, the method comprising the step of scheduling each of the plurality of instructions, determining whether there is a variable for which there is less than a threshold number of physical registers to which that variable may be allocated, and unscheduling a currently scheduled instruction when there is a variable for which there is less than the threshold number of a physical registers to which that that variable may be allocated.

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Bucharest, Romania

Bogdan Batog