Texas Instruments Corporation

Tigmill Technologies, LLC

Bobby D Strong

Kevin M Ovens

Alwin J Tsao

James Fred Salzman

Noel M Russell

Robert C Martin

Christopher Lyle Borst

A fluid sensor system comprises a radio frequency transmitter with adjustable output power, a radio frequency detector proximal to the radio frequency transmitter; a constant current source, and a switch coupled between the radio frequency detector and the constant current source. A method of determining the identity of a fluid using the fluid sensor system includes immersing the sensor system in a first fluid, increasing a transmit power of a radio frequency (RF) transmitter of the fluid sensor system until an RF signal is detected by a RF detector of the fluid sensor system, and determining the transmit power of the RF transmitter that first resulted in a detection of the RF signal by the RF detector to be the transmit power that is required for detecting the RF signal in the first fluid.

Fluid level and composition sensor

Semiconductor devices and manufacturing methods therefor are disclosed, in which conductive fill structures are provided in fill regions in an interconnect wiring layer between conductive wiring structures to facilitate planarization uniformity during metalization processing. One approach employs fill structures of varying sizes where smaller fill structures are formed near wiring regions having high aspect ratio wiring structures and larger fill structures are located near wiring regions with lower aspect ratio wiring structures. Another approach provides fill structures with varying amounts of openings, with fill structures having few or no openings being provided near low aspect ratio wiring structures and fill structures having more openings being located near higher aspect ratio wiring structures.

Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity

The disclosure relates to a method of making a logic circuit wherein the voltage regulators of the ECL circuits, which use resistor ratios, the values of which are difficult to control in the formation of semiconductor circuits, are replaced by a series of diodes, the areas of which are very easy to control in semiconductor fabrication, to set the threshold voltages for the transistors. Embodiments are disclosed using the basic circuit in a stacked configuration to provide AND/NAND operation in addition to the OR/NOR operation of the basic embodiment.

Method of making an ECL logic circuit having diode-clamped loads and

The disclosure relates to a logic circuit wherein the voltage regulators of the ECL circuits, which use resistor ratios, the values of which are difficult to control in the formation of semiconductor circuits, are replaced by a series of diodes, the areas of which are very easy to control in semiconductor fabrication, to set the threshold voltages for the transistors. Diode voltage ratios are very controllable since the diodes change only about 18 millivolts for every factor of two in current change. Thresholds can therefore easily be set in five and ten millivolt increments, this being the procedure utilized herein. Embodiments are disclosed using the basic circuit in a stacked configuration to provide AND/NAND operation in addition to the OR/NOR operation of the basic embodiment.

ECL gates using diode-clamped loads and Schottky clamped reference bias

The disclosure relates to an STL bipolar buffer/driver circuit having a low output impedance for driving capacitive leads and the like wherein the output resistor of the prior art circuits is replaced by an NPN bipolar transistor and a further circuit including a series resistor, schottky diode and schottky clamp transistor for controlling the two output transistors.

STL low impedance buffer/driver

The specification discloses an input transistor (14) which is variable between high and low impedance states in response to input voltage transitions at terminal 10. An output transistor (16) is coupled to the input transistor (14) and is responsive to an input transition at terminal 10 for changing impedance states. Circuitry including a speed up transistor (44) is coupled between the input transistor (14) and output transistor (16) for applying added current to the output transistor (16) to speed the change of impedance state. The circuitry applies added current to output transistor (16) until the output voltage at terminal (18) falls below twice the base-emitter voltage of the output transistor (16).

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Garland, TX, United States of America

Bobby D Strong