Intel Corporation

Bobby B Nikjou

Waleed Khalil

Syed R Naqvi

Xuewen Jiang

Luke A Johnson

Tsung-Yuan Tony Chang

James Tseng

Tsung Yuan Chang

Briefly, in accordance with one embodiment of the invention, a calibration circuit may detect a difference between first and second outputs of a differential output programmable gain amplifier to determine a dc offset at the differential output. In the event an offset is detected, a differential gain of the programmable gain amplifier may be adjusted until the offset is adjusted, or eliminated, to an acceptable predetermined value.

Programmable gain amplifier with self-adjusting offset correction

Briefly, in accordance with one embodiment of the invention, a differential digital-to-analog converter utilized in a transmitter path of a transceiver utilizes a differential R2R architecture. Such a differential digital-to-analog converter may be utilized in higher speed, lower power and higher resolution applications with a higher area efficiency, for example in a WCDMA application.

Differential digital-to-analog converter

Some embodiments of the present invention include a circuit in a wireless transmitter or other apparatus is automatically calibrated using a calibration circuit to accommodate provide a desired characteristic such as a filter response, where the component values of the filter circuit may vary such as in an integrated circuit. In one embodiment, the calibration circuit is coupled to one or more adjustable capacitors in the filter circuit to select a capacitor value so that the filter circuit exhibits the desired filter response. In one particular embodiment, the adjustable capacitor is charged in an RC circuit for each clock cycle at power up. The value of the adjustable capacitor is changed for each clock cycle until the capacitor charges to a level greater than or equal to predetermined reference voltage. When the capacitor is charged to a predetermined reference voltage, a desired capacitance value is indicated, and the adjustable capacitor is maintained at the desired capacitance value to provide the desired filter output. The calibration circuit causes the circuit to be self-calibrating to the desired characteristic such as a desired filter response. Other embodiments are described and claimed.

Self-calibrating tunable filter

Briefly, in accordance with an embodiment of the invention, a method and circuit to reduce intermodulation distortion is provided, wherein the method includes receiving a baseband signal and an interferer signal located in a frequency band and attenuating the interferer signal to reduce intermodulation distortion in the frequency band, wherein the attenuating occurs prior to anti-alias filtering of the baseband signal.

Method and circuit to reduce intermodulation distortion

A power management circuit for use with multiple processors integrated on the same chip where one or more of the processors may run at different clock speeds from the others or be stopped. Clock generation circuitry including a power management unit which provides three power management modes, namely power down mode, idle mode and standby mode, plus separate control of each microprocessor core is utilized. In power down mode, the clocks that drive the general purpose processor core, and the other processors and all peripherals are stopped and the oscillator circuit which provides the clock signals to a circuit used to generate the clock phases used by the processors and peripherals are shut off. In idle mode, only the general purpose microprocessor clock is stopped while the peripherals are running. Standby mode is similar to power down mode in that the clocks that drive the general purpose microprocessor and the other processors and all peripheral clocks are stopped. However, unlike power down mode, during standby mode, the oscillator and the associated clock generation circuitry keep running so the part can wake up quickly. In providing for the separate control of the additional microprocessor cores, in addition to allowing the user to stop the additional cores when they are not needed, the additional cores are stopped when the part comes out of a reset thus preventing the additional cores from executing any program code until after the general purpose microprocessor core has completed its initialization and uploaded application program needed by other cores or processor.

Enhanced power managing unit (PMU) in a multiprocessor chip

A clock generator which utilizes a SDL, power management circuitry, phase drivers and non-overlap logic all integrated on a single chip to output a set of non-overlapped, complementary clock phases for each processor and for on board peripherals. The present invention also has application for use with multiple discrete processors used on an application or system validation board where one or more of the processors may run at different clock speeds from the others or be stopped. The integrated non-overlap logic reduces the clock skewing among various component on the application board, thus, increasing the overall performance of the system. The present invention is specifically directed to clock generation circuitry including a circuit which receives clock phases generated by a SDL, or from a set of frequency dividers and produces non-overlapped clock phases for each on-board processor and for the on-board peripherals.

Low power non-overlap two phase complementary clock unit using

A front end scalar to a frequency multiplier such as a synchronous delay line (SDL) allows the SDL to operate at a single clock frequency for all multiplier coefficients and input frequencies and provides for maximum SDL design margins. A frequency multiplier of this type relies upon a feedback voltage to maintain a desired output clock frequency. So long as the input clock frequency is within predetermined limits, the feedback voltage will maintain the output frequency at a desired frequency for which the SDL has been optimized. As the input frequency approaches the upper or lower limit for which an SDL basic building block has been optimized, it may become impossible for an SDL to provide frequency lock since control voltage is already below or above V.sub.cc /2 due to a lower or a higher input frequency. The invention operates to ensure that the input frequency to the SDL is always close to the frequency for which the SDL has been optimized by changing the input frequency to a frequency which is at or near the frequency for which a SDL has been optimized and thereby eliminate the input frequency dependency of the SDL.

Growing community of inventors

Tempe, AZ, United States of America

Bobby B Nikjou