Texas Instruments Corporation

Bob Todd

Joe R Trogolo

Dan M Mosher

David R Cotton

Larry Latham

Cornelia H Blanton

The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known. For example, the present integrated circuit chip, uses bipolar power transistors instead of vertical DMOS power transistors for power applications. The bipolar power transistors are more rugged and have higher power handling capabilities than DMOS devices. Thus the bipolar transistors can be used for any out-stage configuration, including low side, high side, half bridge and full bridge output circuits. The versatility of the present process flow allows the fabrication of MOSFET, BiMOS, BiCMOS, and bipolar technology either discretely or with high power or low power NPN or PNP devices.

Method of forming complementary bipolar and MOS transistor having power

An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.

Growing community of inventors

Plano, TX, United States of America

Bob Todd