Intel Corporation

Bob Sankman

Chee-Yee Chung

David Gregory Figueroa

Hong Xie

Song-Hua Shi

Richard J Harries

Kris Frutschy

Farzaneh Yahyaei-moayyed

Sudarashan V Rangaraj

Kristopher J Frutschy

Hamid Azimi

Alex Waizman

Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

Apparatuses and methods to enhance passivation and ILD reliability

A flip-chip package is disclosed. The flip-chip package includes a substrate comprising at least one build-up layer. At least one longitudinal trench is formed in at least one build-up layer of the substrate. The at least one longitudinal trench filled with a conductive material. A conductive plane may be disposed at least partially on the at least one longitudinal trench. An insulating layer may cover the conductive plane and, at least in part, at least one build-up layer of the substrate. The solder resist layer may include a plurality of openings partially exposing the conductive plane. A plurality of conductive pads may be disposed on the conductive plane through the plurality of openings. A method for fabricating the flip-chip package is also disclosed.

Flip-chip package and method of forming thereof

Provided are a method, device and system in which, in one embodiment, a socket for an integrated circuit package includes a standoff adapted to engage and support the package in a first position in which the package contact terminals are disengaged from socket contact terminals. The standoff is adapted to move to a second position in which the package contact terminals are engaged with the socket contact terminals. In another embodiment, male and female alignment members guide package contact terminals into engagement with socket contact terminals.

Protected socket for integrated circuit devices

Arrangements are used to supply power to a semiconductor package.

Package stiffener

A guided heating apparatus and a method for using the same is provided. The apparatus includes a guiding enclosure, a supporting piece, and an absorbing piece. The guiding enclosure guides and keeps energy from an energy source within the guiding enclosure. The guiding enclosure is made of a material reflective of the energy. The energy source is either one of a microwave source and an infrared source. The supporting piece is detachably coupled with the guiding enclosure and is made of a material transparent to the energy. The absorbing piece is coupled to and supported by the supporting piece within the guiding enclosure. The absorbing piece is made of at least one material that absorbs the energy and transfers the energy to an object to be heated. The absorbing piece has a predetermined composition that controls an energy absorption rate of the absorbing piece.

Guided heating apparatus and method for using the same

A system and method for embedding power and ground planes in a pin grid array (PGA) socket is provided. Integrated circuit pins are inserted into multiple insertion holes of varying dimensions in the power and ground planes. When the cover of the socket is slidably moved, power pins touch the power plane and ground pins touch the ground plane. Decoupling capacitors are also affixed to the substrate. Thus, the power delivery performance of the overall central processing unit (CPU) package is improved. Moreover, the power and ground planes enhance the mechanical strength of the socket which reduces warpage.

System and method for package socket with embedded power and ground planes

An integrated circuit package is provided that includes a multi-layer organic substrate. The substrate has conductive vias provided between isolated conductive layers. The vias are formed using a laser to cut through a dielectric layer separating the conductive layers. External interconnects in the form of T-shaped pins are soldered to the substrate of the integrated circuit package. An integrated circuit can be attached to the substrate using a flip-chip technique.

Integrated circuit package

A semiconductor device package includes multiple build-up layers of metal sandwiching non-conductive layers. The metal layers include apertures, or degassing holes. A manual method and a computer-implemented method for designing the semiconductor device packages includes stepping polygons across a representation of a conductive layer. A signal routing layer that includes signal traces is then superimposed on the conductive layer. Signal traces overlap the polygons creating regions of intersection that can be enlarged. Regions of intersection are removed from the polygons and the remaining polygon area is designated as apertures in the conductive layer. A semiconductor device package and packaged integrated circuit includes apertures in a conductive layer such that the apertures generally form a radial pattern outward from a region on the package. Signal traces also traverse the package generally radially outward such that the traces and the apertures do not overlap. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by trace.

Growing community of inventors

Phoenix, AZ, United States of America

Bob Sankman