International Business Machines Corporation

Bob H Yun

Robert K Cook

Seshadri Subbanna

Roger L Verkuil

Manu J Tejwani

Paul Andrew Ronsheim

Ronald W Knepper

Russell C Lange

Min-Su Fung

William Andrew Keenan

Subodh K Kulkarni

Krishnamur Venkataraman

Richard A Corcoran

Demetrios Michaelides

An apparatus for measuring charge in an oxide layer overlying a silicon substrate containing very high density product chips characterized by thick oxides and high substrate doping levels in the field regions. A specially designed extremely thin conductive probe is pressed against the oxide layer whose charge is to be measured. A bias is applied to the probe for biasing the underlying silicon surface into accumulation or inversion. An intensity modulated light beam is focussed at the point of probe contact. The resulting amplitude modulated photovoltage is detected and applied to a computer to derive the value of the oxide charge therefrom.

Photovoltaic oxide charge measurement probe technique

A circuit for generating a negative voltage includes: a bipolar transistor including, a) an N type collector region, b) a P type base region, and c) an N type emitter region, the base region width between the emitter region and the collector region being less than about 5,000 angstroms and the dopant concentration of the base region being in the range of about 1-10.times.10.sup.18 atoms/cm.sup.3 ; means for applying a reference potential to the base region; and means for applying a bias potential to the emitter region so as to generate a negative output potential at the collector region. The circuit can likewise comprise a PNP bipolar transistor biased to generate a negative voltage. The circuit can be used on integrated circuit chips to provide a complementary voltage, thereby obviating the requirement for separate, complementary power supplies.

Bipolar transistor using emitter-base reverse bias carrier generation

A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.

Method for controlling interfacial oxide at a

An apparatus for measuring the surface potential and impurity concentration in a semi-conductor body by monitoring the current flowing in a semiconductor body when the body is biased with a ramp voltage above its flat band voltage and summing the monitored current with the ramp voltage biasing the body. The apparatus provides direct measurement of surface potential and impurity concentration in a semiconductor structure and is especially useful in metal insulator semiconductor (MIS) structures.

Automated channel doping measuring circuit

A method is shown for forming ultra fine, deep dielectric isolation in a silicon body. The method involves forming a first layer of material on the silicon body over a first set of alternately designated device regions. A conformal coating is deposited over the first layer and on the silicon body included in a second set of alternately designated device regions and the designated isolation regions. The thickness of the conformal coating is chosen to be substantially the width of the planned isolation between device regions. A second layer is then deposited over the conformal coating. The first layer and conformal coating are composed of different materials. The topmost surface comprising of the second layer and the conformal coating is planarized by removing partially the second layer and conformal coating from the first layer wherein the second set of alternately designated device regions in the silicon body are covered by the conformal coating and the second layer with portions of the conformal coating separating the covers for the first and second set of device regions. The portions of the conformal coating separating the covers are removed down to the silicon body over the designated isolation regions. A groove is then etched in the silicon body using the covers as the etch mask. The groove is etched to the desired depth of the dielectric isolation in the designated isolation regions and then is filled typically by thermal oxidation.

Method for forming ultra fine deep dielectric isolation

An apparatus for measuring and quantitatively determining the number of surface states at or near the insulator-semiconductor interface in a metal-insulator-semiconductor (MIS) structure by injecting a controlled amount of charge into the insulator to induce a change in the surface state occupancy and measuring simultaneously and directly the amount of charge injected into the insulator, the charge so induced in the semiconductor and in the surface states and the corresponding change in the surface potential of the semiconductor induced by the injected charge.

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Hopewell Junction, NY, United States of America

Bob H Yun