Tektronix, Inc.

Bipolar Integrated Technology, Inc.

Bob Elkind

Kenneth M Ainsworth

Gregory F Taylor

James R Peterson

James L Tallman

Gilbert A Hoffman

Jay D Lessert

Howard A Landsman

David K Fibush

Gary Sargeant

A video error/distortion checker generates a difference signal from an input repetitive digital signal and a reference data signal corresponding to the input repetitive digital signal. The difference signal is compared with maximum and minimum threshold values to generate an error signal when the difference signal exceeds either threshold value. The difference signal also is used to generate a running range value that is compared with a total range value to produce the error signal when during one iteration of the repetitive digital signal the difference signal exceeds a specified range defined by the total range value. The error signal is suitably displayed, either visually or alphanumerically or both, so that an operator may recognize the type, severity and location of errors in the repetitive digital signal.

Video error/distortion checker

Generation of digital cursors for serial digital television waveform monitors includes inputting hexadecimal values for the cursors by an operator via a front panel. The hexadecimal values are received by a microprocessor which loads them into appropriate registers of a co-processor. The outputs of the cursor registers in the co-processor are input to respective inputs of a multiplexer together with a digital signal representing a serial digital television signal. A select signal for the multiplexer is generated by a selection circuit that is enabled by a digital cursor ON command when the waveform monitor is in a cursor mode. The selection circuit at predetermined locations of the digital signal generates the select signal so that the appropriate cursor values are inserted into the digital signal at those locations. The processed digital signal from the co-processor is then converted to analog, filtered, and displayed on a display device to present a waveform representing the serial digital television signal together with the digital cursors.

Digital cursors for serial digital television waveform monitors

A digital audio waveform display is presented on a digital video waveform display instrument using the video waveform display circuitry. A decoder extracts embedded digital audio data from a digital video signal. The digital audio data is stored in a buffer memory. N digital audio data words, corresponding to N samples of the video data representing a video line for display, are read from the buffer memory at a video sample rate and input to the video waveform display circuitry. The video waveform display circuitry includes a digital to analog converter operating at the video sample rate and an analog video reconstruction filter which provides amplitude values for a swept display device.

Digital audio waveform display on a video waveform display instrument

A bright video line select display for a waveform monitor is achieved by storing a selected line from a video frame of a digital video input signal. The stored selected line is iteratively substituted for a plurality of video lines during the vertical interval of the digital video input signal. When line select mode is selected, those video lines during the vertical interval are displayed as a waveform, resulting in a brighter display of the selected video line.

Bright video line select display

Error detection for digital television equipment that strips away the vertical and horizontal intervals of a digital video signal so that only the active picture portion of the digital video signal is determined by a digital test signal generated from the digital video signal. The digital test signal has replaced at a predetermined location in the active picture portion of the digital video signal one or more video data words with data values that represent check word data for the active picture portion. The check word data may be inserted into the beginning of one of the horizontal lines of the active picture portion of the next field, or may be modified and inserted into the end of the last line of the active picture portion of the same field of the digital video signal. A receiving instrument processes the output of the digital television instrument under test to generate active picture check word data. The active picture check word data is compared either with the check word data extracted from the predetermined location in the active picture portion of the digital test signal or with a predetermined value to determine whether there were any digital errors in processing of the digital test signal by the digital television equipment.

Error detection for digital television equipment

In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recorded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder (CSA) cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier and divider are pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include two-speed internal clocking for operation and testing, two-node clock stopping and distributed buffering of system clock signals.

Floating point processor with internal free-running clock

In a high-speed binary multiplier circuit, the multiplicand is segmented into a series of 8-bit slices and the multiplier is modified-Booth recoded into 3-bit groups. The corresponding partial product terms are reduced in a regular array of small carry-save adder cells. Iterative use of the CSA array provides the Wallace tree function in one-seventh the chip area or number of adders of a conventional implementation. The multiplier is pipelined internally, driven by a fast, two-phase internal clock that is transparent to the user. The internal clock stops and restarts upon loading new operand and instruction data to synchronize the internal clock to the system clock. Other aspects of the invention include high-speed absolute value subtract circuitry for exponent calculations and normalizing floating point results.

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Gaston, OR, United States of America

Bob Elkind